Technical Specifications
440 processor core with 32K instruction cache/32K data cache
CoreConnect™ bus architecture
Up to 667MHz performance
Up to 1,334 DMIPS
5 stage FPU with 2.0 MFLOPS/MHz
NAND Flash controller supporting 1 to 4 banks of NAND Flash
memory devices; Boot-from-NAND supported
USB 1.1 Host and Device Controllers and PHYs
USB 2.0 Device Controller
Two 10/100 Ethernet MACs
32-bit PCI controller, 66MHz (PCI v2.2 compliant)
32-bit DDR1 SDRAM Controller for DDR200/266 operation
SPI serial interface 4-channel DMA
Universal Programmable Interrupt Controller
On-chip Peripherals including:
Four serial ports
Master and slave IIC controller
Up to 53 general purpose I/Os
3W estimated typical power dissipation at 533MHz
Target Applications
Imaging
Industrial Control
Networking
【文件名】:061230@52RD_PPC440EP_DS2002_v1_24.pdf
【格 式】:pdf
【大 小】:1246K
【简 介】:
【目 录】: