本人有一程序逻辑仿真通过,但时序仿真有问题,请高手指点

6799037

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fenpin is  
port(clk :in std_logic;
     ad_clk,fifo_clk :out std_logic;
     ad_fif out std_logic);
end;
architecture clk of fenpin is
begin
process(clk)
variable x :std_logic:='0';
begin
if clk'event and clk='1'  then
    x:=not x;
end if;
ad_fifo<=x;
ad_clk<=x;
fifo_clk<=x;
end process;
end clk;