cmos fast setting pll for ofdm uwb application

comsrf

A CMOS phase-locked loop (PLL) which synthesizes
frequencies between 6.336 and 8.976 GHz in steps of 528 MHz and
settles in approximately 150 ns is presented. The proposed PLL
can be employed as a building block for a frequency synthesizer
which generates a seven-band hopping carrier for multiband
orthogonal frequency division multiplexing (MB-OFDM) ultrawideband
(UWB) radio. To achieve fast loop settling, integerarchitecture
that operates with 528-MHz reference frequency
is implemented and a wideband active-loop filter is integrated.
An improved phase-frequency detector (PFD) is proposed for
faster loop settling. To reduce reference sidebands, a feedback
circuit using replica bias is implemented in the charge pump. I/Q
carriers are generated by two cross-coupled LC VCOs. The output
current of the charge pump is controlled to compensate for the
VCO gain nonlinearity and a programmable frequency divider
(12 17) that reliably operates at 9 GHz is designed. Fabricated
in 0.18- m CMOS technology, the PLL consumes 32 mA
from a 1.8-V supply and achieves phase noise of 109.6 dBc/Hz
at 1-MHz offset and spurs of 52 dBc.
Index Terms—Phase-frequency detector, phase-
【文件名】:061223@52RD_fast setting PLL.pdf
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