pll jitter simulation

comsrf

A methodology is presented for modeling the jitter in a Phase-Locked Loop (PLL) that
is both accurate and efficient. The methodology begins by characterizing the noise
behavior of the blocks that make up the PLL using transistor-level simulation. For each
block, the jitter is extracted and provided as a parameter to behavioral models for inclusion
in a high-level simulation of the entire PLL. This approach is efficient enough to be
applied to PLLs acting as frequency synthesizers with large divide ratios.


【文件名】:061215@52RD_modelingjitterinpll.pdf
【格　式】:pdf
【大　小】:347K
【简　介】:
【目　录】: