Design and Implementation of a Link Level Adaptive Software Radio

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Design and Implementation of a Link Level Adaptive Software Radio
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目录
CHAPTER 1 INTRODUCTION.......................................................................................................... 1
BRIEF OVERVIEW OF THE RDRN2 PROJECT........................................................................................ 1
RDRN2 COMMUNICATION SYSTEMS OVERVIEW................................................................................ 3
CHAPTER 2 BACKGROUND............................................................................................................ 7
SUPER-HETERODYNE RECEIVER........................................................................................................ 10
DIGITAL RADIOS & SOFTWARE RADIOS ............................................................................................ 12
Digital IF and Subsampling Receivers ...............................................................................................15
Decimation ........................................................................................................................................17
TRANSCEIVER PERFORMANCE METRICS............................................................................................ 19
CHAPTER 3 SYSTEM DESCRIPTION .......................................................................................... 22
TRANSMITTER REQUIREMENTS.......................................................................................................... 22
RECEIVER REQUIREMENTS ................................................................................................................ 24
MULTIPLE ACCESS SCHEME AND BANDWIDTH UTILIZATION ............................................................ 26
LINK BUDGET ................................................................................................................................... 29
POWER REQUIREMENTS.................................................................................................................... 32
THE CONTROL BUSSES ...................................................................................................................... 36
CHAPTER 4 TRANSMITTER IMPLEMENTATION................................................................... 40
Baseband to IF ............................................................................................................................. 40
Input Stage & Formatting...................................................................................................................42
RC Filters ..........................................................................................................................................42
IF to RF....................................................................................................................................... 43
Quadrature Modulator ........................................................................................................................43
240 MHz PLL and VCO Carrier Generation......................................................................................44
Amplification and SAW Filter ...........................................................................................................45
Programmable Attenuators.................................................................................................................46
RF Section ................................................................................................................................... 46
Mixer ......................................................................................................................................47
LO Generation...................................................................................................................................48
RF Mixer ...........................................................................................................................................48
RF Amplification and Filtering ..........................................................................................................48
Quad-Sectored Patch Antenna Array..................................................................................................49
CHAPTER 5 RECEIVER IMPLEMENTATION ........................................................................... 51
Signal Level Table.............................................................................................................................52
Noise Figure Graph ............................................................................................................................53
RF Receiver................................................................................................................................. 54
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Patch Antenna sub-Assembly.............................................................................................................54
RF Mixer ...........................................................................................................................................55
LO Generation...................................................................................................................................55
IF to ADC.................................................................................................................................... 56
Low Pass Filter and Amplification Section ........................................................................................56
SAW Filter ........................................................................................................................................57
AGC Amplifier..................................................................................................................................57
IF Amplification Chain ......................................................................................................................59
ADC to Baseband........................................................................................................................ 59
ADC Input Conditioning ....................................................................................................................59
Analog to Digital Converter (ADC) ...................................................................................................59
Signal Processing1 Altera...................................................................................................................62
Digital Quadrature Tuner, the HSP50110 ..........................................................................................63
Signal Processing2 Altera...................................................................................................................65
Digital Costas Loop, the HSP50210...................................................................................................65
CHAPTER 6 SUMMARY AND CONCLUSIONS .......................................................................... 69
FUTURE WORK ................................................................................................................................. 69
REFERENCES ................................................................................................................................... 71
APPENDIX A...................................................................................................................................... 73
JUMPER SETTINGS & HEADERS.......................................................................................................... 74
CONNECTOR DESCRIPTION AND INPUT/OUTPUT LEVELS ................................................................... 77
PROGRAMMING THE PLLS ................................................................................................................. 79
PROGRAMMING THE HARRIS CHIPSET................................................................................................ 81
PROGRAMMING THE CPLDS .............................................................................................................. 85
APPENDIX B...................................................................................................................................... 86
RF SCHEMATICS............................................................................................................................... 87
IF AND DIGITAL SECTION SCHEMATICS............................................................................................. 98
ALTERA CPLD COMBINATION LOGIC DIAGRAMS........................................................................... 119
BILL OF MATERIALS ........................................................................................................................ 134
DELTA LIST FOR IFDIG REV1.0 ....................................................................................................... 137

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