请教大虾关于浮点运算

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请教大虾关于浮点运算
  我使用的是ise 8.1 我想利用其中的IP COER “  FLOATING-POINT OPERATOR V1.0”实现32位的浮点乘法。程序综合可以过 但是用MODESIM 仿真时出现“LOADING”错误，下面是我编的一个简单的乘法，希望各位大虾帮忙看看，解决问题。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity vs_f_mult is
    Port ( rst : in  std_logic;
        clk64m : in std_logic;
          dina : in std_logic_vector(23 downto 0);
          dinb : in std_logic_vector(23 downto 0);
          dout : out std_logic_vector(23 downto 0));
  
end vs_f_mult;

architecture Behavioral of vs_f_mult is
  component signed_multiplier
port (
a: IN std_logic_VECTOR(17 downto 0);
b: IN std_logic_VECTOR(17 downto 0);
  OUT std_logic_VECTOR(18 downto 0));
  END component;

signal mouttem: std_logic_vector(18 downto 0);
signal mout: std_logic_vector(18 downto 0);
signal mana: std_logic_vector(17 downto 0);
signal manb: std_logic_vector(17 downto 0);
signal expa: std_logic_vector(5 downto 0);
signal expb: std_logic_vector(5 downto 0);
signal exp : std_logic_vector(6 downto 0);
begin
  mana <= dina(23 downto 6);
manb <= dinb(23 downto 6);
expa <= dina(5 downto 0);
expb <= dinb(5 downto 0);

mout_mult:signed_multiplier
port map(mana,manb,mouttem);

  process(rst,clk64m)
    variable expv: std_logic_vector(6 downto 0);
begin
    --if rst='1' then
      --dout<= (others=>'0');
    --expv:= (others=>'0');
      if rising_edge(clk64m) then
      mout <= mouttem;
    exp <= (expa(5)&expa) + (expb(5)&expb);
    if (exp<-31 or mout=0) then
      dout <= "000000000000000000100000";
          elsif mout(18)/=mout(17) then
        expv:= exp +1;
    dout <= mout(18 downto 1)&expv(5 downto 0);
          else
        dout <= mout(17 downto 0)&exp(5 downto 0);
          end if;
  end if;
end process;

end Behavioral;

谢谢！！！！！！！！！！！！！！！！！！！！！