VHDL新手问题

hmq

请问各位，怎样用VHDL描述一个可变输入数目（用generic）的multiplexer?
我写不出architecture

library        ieee;
use        ieee.std_logic_1164.all;
package mytype is
        type vector_array is array(natural range<>) of std_logic_vector(7 downto 0);
end package;

library        ieee;
use        ieee.std_logic_1164.all;
use               work.mytype.all;

entity mux501 is
        generic(n: integer:= 2);         
        port(din: in vector_array(0 to 2**n-1);
        sel: in integer range 0 to 2**n-1;
        dout: out std_logic_vector(7 downto 0));
end mux501;

architecture mux501_arch of mux501 is
begin
    --不知道怎么写？
end mux501_arch;

不胜感谢！！！！