designing_safe_verilog

donn

【文件名】:0682@52RD_designing_safe_verilog.rar
【格　式】:rar
【大　小】:116K
【简　介】:One of the strengths of Synplify is the Finite State Machine compiler.  This is a powerful feature that not only has the ability to automatically detect state machines in the source code, and implement them with either sequential, gray, or one-hot encoding.   But also perform a reachability analysis to determine all the states that could possibly be reached, and optimize away all states and transition logic that can not be reached.Thus, producing a highly optimal final implementation of the state machine.
【目　录】:无目录