a non-linear adaptive

bitgyn

This paper presents the study of a non-linear adaptive
filter implementation using VHDL, targeted to FPGA
devices. The paper presents the basic structure of the
filter, as well as a discussion on the area and speed results
with different multipliers. A full 8-tap filter was
synthesized with different architecture choices.
the input signal itself) to calculate the output signal.
Equation 1 represents the convolution executed in the first
phase, when the output signal y[n] is calculated as a
function of the input signals (x[n]..x[n-i]) and the filter
coefficients (h1[0]..h1, h2[0]..h2, h3[0]..h3,