The LEON-2 Processor User’s Manual & vhdl source code

kevin_liao

The LEON VHDL model implements a 32-bit processor conforming to the IEEE-1754
(SPARC V8) architecture. It is designed for embedded applications with the following
features on-chip: separate instruction and data caches, hardware multiplier and divider,
interrupt controller, debug support unit with trace buffer, two 24-bit timers, two UARTs,
power-down function, watchdog, 16-bit I/O port and a flexible memory controller. New
modules can easily be added using the on-chip AMBA AHB/APB buses. The VHDL model is fully synthesisable with most synthesis tools and can be implemented on both FPGAs and ASICs. Simulation can be done with all VHDL-87 compliant simulators.

【文件名】:06725@52RD_leon_vhdl.rar
【格　式】:rar
【大　小】:857K
【简　介】:The LEON VHDL model implements a 32-bit processor conforming to the IEEE-1754
(SPARC V8) architecture. It is designed for embedded applications with the following
features on-chip: separate instruction and data caches, hardware multiplier and divider,
interrupt controller, debug support unit with trace buffer, two 24-bit timers, two UARTs,
power-down function, watchdog, 16-bit I/O port and a flexible memory controller. New
modules can easily be added using the on-chip AMBA AHB/APB buses. The VHDL model is fully synthesisable with most synthesis tools and can be implemented on both FPGAs and ASICs. Simulation can be done with all VHDL-87 compliant simulators.
【目　录】: