multiple clock design

Hedda

【文件名】:06531@52RD_multiclock_design.rar
【格　式】:rar
【大　小】:273K
【简　介】:This whitepaper discusses DFT and ATPG issues that commonly occur for designs with multiple clock domains. Multiple vs. single clock in test mode and different scan cell structures will be discussed with respect to the different modes of operation in a scan based test. Different pattern generation methods will be discussed with respect to safe operation, pattern count, and test generation runtime.
【目　录】:
Abstract
Problem Definition
Test Solutions
Hardware
Mux-DFF: Using one clock in test mode
Mux-DFF: Using multiple clocks in test mode
Mux-DFF: Scan chain ordering
LSSD
D-mimic
ATPG
Pulsing one clock per pattern
Utilizing clock independence
Pulsing clocks sequentially
Recommendations and Conclusions
Appendix A –D-mimic cells in DFTAdvisor and FastScan
Type 1 D-mimic (Figure 6)
Type 2 D-mimic (Figure 8)