集成电路中互连线的寄生效应

Gill

【文件名】:06531@52RD_十 Benchmarks for interconnect parasitic resistance and capacitance.rar
【格　式】:rar
【大　小】:463K
【简　介】:Interconnect parasitics are dominating circuit performance,
signal integrity and reliability in IC design. Copper/low-k
process effects are becoming increasingly important to
accurately model interconnect parasitics. Even if the
interconnect process profile is accurately represented,
approximations in parasitic extraction could cause large
errors. Typically, researchers and designers have been using
pre-defined set of structures to validate the accuracy of
interconnect models and parasitic extraction tools. Unlike
industry benchmarks on circuits such as MCNC benchmarks,
no benchmarks exist for interconnect parasitics. This paper
discusses the issues in accurate interconnect modeling for
130nm and below copper/ultra low-k technologies. A set of
benchmark structures that could be used to validate accuracy
and compare parasitic extraction tools is proposed. Silicon
results from 130nm technology are presented to illustrate the
usefulness of these benchmarks. Results of application of these
benchmarks to compare parasitic extraction tools are
presented to demonstrate systematic validation of resistance
【目　录】:
1. Introduction
2. Accurate Interconnect Modeling
3. Parasitic RC Extraction
4. Benchmark Proposal
5. Results
6. Summary
7. References