A Verilog HDL Test Bench Primer.pdf

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【文件名】:06524@52RD_A Verilog HDL Test Bench Primer.pdf
【格　式】:pdf
【大　小】:65K
【简　介】:
【目　录】:Introduction ...........................................................................................................1
Overview...............................................................................................................1
The Device Under Test (D.U.T.) ...........................................................................1
The Test Bench ....................................................................................................1
Instantiations.........................................................................................................2
Figure 1- DUT Instantiation.............................................................................................2
Reg and Wire Declarations...................................................................................2
Figure 2 – Reg and Wire Declarations.............................................................................3
Initial and Always Blocks.......................................................................................3
Figure 3 – An Initial Block Example...............................................................................3
Figure 4 – An Always Block Example ............................................................................4
Initialization .....................................................................................................................4
Delays..............................................................................................................................4
Clocks and Resets ............................................................................................................4
Assign Statements................................................................................................4
Figure 5- An Assign Example..........................................................................................5
Printing during Simulations ...................................................................................5
$display...........................................................................................................................5
Figure 6- $display Example .............................................................................................5
$monitor..........................................................................................................................5
Figure 7- Using $monitor.................................................................................................5
Tasks ....................................................................................................................6
Figure 8- An Example of a Task – load_count ................................................................6
Count16 Simulation Example................................................................................6
Table 1- Simulation Steps................................................................................................6
Figure 9 – The Transcript Window for the Count16 Simulation....................................8
Figure 10 – The Simulation Waveform Window for the Count16 Simulation................8
Gate Level Simulations.........................................................................................9
Appendix A- The count16.v Verilog Source File ............................................................9
Appendix B- The cnt16_tb.v Verilog Test Bench Source File ......................................10
Reference Materials............................................................................................12