Modeling Jitter in PLL-based Frequency Synthesizers

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【文件名】:06518@52RD_Modeling Jitter in PLL-based Frequency Synthesizers.rar
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【简　介】:Phase-locked loops (PLLs) are used in wireless receivers to implement a variety of functions, such as frequency synthesis, clock recovery, and demodulation. One of the major concerns in the design of PLLs is noise or jitter performance. Jitter from the PLL directly acts to degrade the noise floor and selectivity of a transceiver.
Demir proposed an approach for modeling PLLs whereby a PLL is described using high level behavioral models [1,2]. The models are written such that they include jitter in an efficient way. He also devised a powerful new simulation algorithm that is capable of characterizing the circuit-level noise behavior of blocks that make up a PLL that is based on solving a set of nonlinear stochastic differential equations [3,5]. Finally, he gave formulas that can be used to convert the results of the noise simulations on the individual blocks into values for the jitter parameters for the corresponding behavioral
models [6]. This approach provides accurate and efficient prediction of PLL jitter behavior once the noise behavior of the blocks has been characterized. However, it requires the use of an experimental simulator that is not readily available.
【目　录】:
1 Introduction
2 Frequency Synthesis
3 Jitter
4 Synchronous Jitter
5 Accumulating Jitter
6 Jitter of a PLL
7 Modeling PLLs with Jitter
8 Simulation and Analysis
9 Example
10 Conclusion