A Hierarchical Rail Analysis Flow for Multimillion Gate SoCs

Olive

【文件名】:06516@52RD_Power Optimization.rar
【格　式】:rar
【大　小】:833K
【简　介】:Design teams have developed manual approaches to estimating power and designing power networks for their SoCs. Typically, the team combines library vendor and fab vendor design guidelines with engineering estimation and floorplanning to produce robust strap-based and mesh-based power networks.
As design libraries move to smaller geometries, the effects of supply variation on gate delay and SoC performance become more pronounced and can no longer be margined from estimations. A more automated and repeatable signal integrity analysis approach for Rail Analysis and EM analysis sign-off is required.
【目　录】:
1.0 Objective
2.0 Rail Analysis Flow Overview
3.0 IR Drop and EM Analysis Flow Example and Metrics
4.0 Lessons Learned
5.0 Problems Encountered and Their Solutions
6.0 Summary and Recommendations
7.0 Future Work
8.0 Acknowledgements
9.0 References
10.0 Appendix