时钟树综合

Adelaide

【文件名】:06512@52RD_clock_tree.rar
【格　式】:rar
【大　小】:43K
【简　介】:In synchronous design, the clock net needs to be routed with great precision since the clock net delay  also determines the maximum clock frequency on which a chip can operate. An important issue of the  clock net design is buffering, which is necessary to control “clock skew” and delay. The clock skew is the maximum difference among the arrival times of the clock signals. The objective of this problem concerns about the re -selection of buffers in the clock tree so that the given constraint of the clock skew is met and at the same tim e the clock delay (the maximum arrival time among clock signals) is minimized.   
【目　录】:
1. Introduction
2. Delay Calculation Using Non-linear Delay Model (NLDM)
3. Assumption and Input/Output Specification
4 .Examples of Input Formats
5. Evaluation