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【文件名】:06511@52RD_golson_snug01.rar
【格 式】:rar
【大 小】:96K
【简 介】:A wealth of new hierarchical compile strategies have become available in the last few years. This paper will compare area, speed, and compile time for several large designs using a variety of hierarchical compile strategies: top-down compile, top-down simple compile, bottom-up with
default constraints, bottom-up with hand-crafted constraints, and ACS (Automated Chip Synthesis).
【目 录】:无目录
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