关于 状态机State Machine 设计的2个文档

Juliet

【文件名】:06511@52RD_State Machine.rar
【格　式】:rar
【大　小】:237K
【简　介】:一、Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is a great paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper also offers in-depth background concerning the origin of specific state machine types.This paper, "State Machine Coding Styles for Synthesis," details additional insights into state machine design including coding style approaches and a few additional tricks.
二、State machine design techniques for Verilog and VHDL
【目　录】:
一、无目录
二、1.0 Introduction
2.0 Basic HDL coding
3.0 State assignment
4.0 Coding state transitions
5.0 Outputs
6.0 Inputs
7.0 FSM extract
8.0 Timing constraints
9.0 Synthesis strategies
10.0 Compile results
11.0 Hints, tips, tricks, mysteries
12.0 Acknowledgments
13.0 References
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