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[IC设计资料] ova验证技术文档

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发表于 2006-4-26 15:01:00 | 显示全部楼层 |阅读模式
【文件名】:06426@52RD_ova_wp.rar
【格 式】:rar
【大 小】:45K
【简 介】:The amount of time and manpower that is invested in finding and removing bugs is growing faster than the investment in creating the design. In addition, the raw dollar cost of a chip re-spin is also increasing. Problems with chip functionality are caused by incomplete or unclear specifications or just simple human coding errors.
Current verification techniques are inadequate at catching these errors and eliminating them.
Consider the case where you have embedded a core in a system-on-a-chip (SoC). If you are just checking signals at the chip level, then you may not catch a bug that is caused by an improper protocol to the embedded core. If the protocols were constantly being monitored, then when the violation occurs the simulation would immediately respond with an assertion failure, and the real cause of the problem can be investigated.
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