A Recipe for MultiMillion Gate ASIC Verification

Adelaide

【文件名】:06426@52RD_ARecipeforMulti-MillionGateASICVerification.rar
【格　式】:rar
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【简　介】:Employers and ultimately customers are screaming for larger and more complex designs in less and less time. Silicon vendors are saying a big
YES with capacities that can handle just about anything one can throw at
them. EDA tools are slowly catching up to handle the deep submicron
world of ultra-dense designs.
But before we can ship these large multi-million gate ASICs, we have to
verify that they are functionally correct. The task of verification has
grown to have a life of its own. The typical verification effort is now estimated
to be up to 70% of the overall effort, or as Figure 1 shows, that for
each line of RTL code, 5-10 lines of verification code will need to be
written.
【目　录】:
1.0 Introduction
2.0 Key Ingredients
3.0 Verification Planning and Documentation
4.0 Design Management, Revision Control and Scripting
5.0 Verification Infrastructure
6.0 Who Does What?
7.0 Conclusion