[IC设计资料] Getting start with systemverilog for design and verification!!

发表于 2006-4-25 14:52:00 | 显示全部楼层 |阅读模式

【文件名】:06425@52RD_Getting start.zip
【格　式】:zip
【大　小】:151K
【简　介】:VERIFICATION GETTING DESIGN

【目　录】:无目录

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