[分享]IEEE 1800-2005 SystemVerilog IEEE标准（IEEE正式标准）

crystaless

【文件名】:06425@52RD_IEEE Std 1800-2005[1][1].part1.rar
【格　式】:rar
【大　小】:2048K
【简　介】:The purpose of this standard is to provide the electronic design automation (EDA), semiconductor, and system design communities with a well-defined and official IEEE unified hardware design, specification, and verification standard language. The language is designed to coexist and enhance the hardware description languages (HDLs) presently used by designers while providing the capabilities lacking in those languages.
SystemVerilog is a unified hardware design, specification, and verification language that is based on the Accellera SystemVerilog 3.1a extensions to the Verilog HDL [B1]a, published in 2004. Accellera is a consortium of EDA, semiconductor, and system companies. IEEE Std 1800 enables a productivity boost in design and validation and covers design, simulation, validation, and formal assertion-based verification flows.
SystemVerilog enables the use of a unified language for abstract and detailed specification of the design,specification of assertions, coverage, and testbench verification that is based on manual or automatic methodologies.
SystemVerilog offers application programming interfaces (APIs) for coverage and assertions, avendor-independent API to access proprietary waveform file formats, and a direct programming interface (DPI) to access proprietary functionality. SystemVerilog offers methods that allow designers to continue to use present design languages when necessary to leverage existing designs and intellectual property. This standardization project will provide the VLSI design engineers with a well-defined IEEE standard that meets
their requirements in design and validation and enables a step function increase in their productivity. This standardization project will also provide the EDA industry with a standard to which they can adhere and which they can support in order to deliver their solutions in this area.
【目　录】:
1. Overview
2. Normative references
3. Literal values
4. Data types
5. Arrays
6. Data declarations

crystaless

【文件名】:06425@52RD_IEEE Std 1800-2005[1][1].part2.rar
【格　式】:rar
【大　小】:1496K
【简　介】:
【目　录】:

crystaless

【文件名】:06425@52RD_SystemVerilog Basic Training.zip
【格　式】:zip
【大　小】:389K
【简　介】:All slides in this presentation are copyrighted by Sunburst Design, Inc. of Beaverton,Oregon and are solely intended for distribution to, and use by SystemVerilog Symposium attendees. All rights reserved. No material from this seminar may be used by any individual or company for training without the express written permission of Sunburst Design, Inc.
【目　录】:无目录

fanb1983

lz太不厚道，分成这么多收钱[em27]

frankqs

太不厚道了
这个就要7块钱呀！