异步多时钟设计的综合实现

Hannahey

【文件名】:06417@52RD_异步多时钟的设计实现.rar
【格　式】:rar
【大　小】:159K
【简　介】:Most college courses teach engineering students prescribed techniques for designing completely synchronous (single clock) logic. In the real ASIC design world, there are very few single clock designs. This paper will detail some of the hardware design, timing analysis, synthesis and
simulation methodologies to address multi-clock designs.
This paper is not intended to provide exhaustive coverage of this topic, but is presented to share techniques learned from experience.
【目　录】:
1.0 Introduction
2.0 Metastability
3.0 Synchronizers
4.0 Static Timing Analysis
5.0 Clock Naming Conventions
6.0 Design Partitioning
7.0 Synthesis Scripts & Timing Analysis
8.0 Synchronizing Fast Signals Into Slow Clock Domains
9.0 Passing Multiple Control Signals
10.0 Data-Path Synchronization
11.0 FIFO Design
12.0 Simulation Issues
13.0 Conclusions