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【文件名】:06412@52RD_全数字FM接收机.rar
【格　式】:rar
【大　小】:657K
【简　介】:The design of the All Digital FM Receiver circuit in this project uses Phase Locked Loop (PLL) as the main core. The task of the PLL is to maintain coherence between the input (modulated) signal frequency, i ω and the respective output frequency, o ω via phase comparison. This self-correcting ability of the system also allows the PLL to track the frequency changes of the input signal once it is locked.
Frequency modulated input signal is assumed as a series of numerical values
(digital signal) via 8-bit of analog to digital conversion (ADC) circuit. The FM
Receiver gets the 8 bit signal every clock cycle and outputs the demodulated signal.
The All Digital FM Receiver circuit is designed using VHDL, then simulated and
synthesized using ModelSim SE 6 simulator and Xilinx ISE 6.3i, respectively. FPGA implementation also provided, here we use Virtex2 device. The real measurement is done using ChipScope Pro 6.3i.
【目　录】:
1. Introduction
2. Architecture Description
3. Functional Explanation
4. Critical Path Speed and Circuit Area
5. Appealing Point and Originality
6. HDL Codes
7. Simulation Waveform
8. FPGA Implementation
9. Closing


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