Quick Reference for Verilog HDL

Oliverneil

【文件名】:06411@52RD_VerilogQuickRef.rar
【格　式】:rar
【大　小】:60K
【简　介】:This is a brief summary of the syntax and semantics of the Verilog Hardware Description Language. The summary is not intended at being an exhaustive list of all the constructs and is not meant to be complete. This reference guide also lists constructs that can be synthesized. For any clarifications and to resolve ambiguities please refer to the Verilog Language Reference  Manual, Copyright 1993 by Open Verilog International,
Inc. and synthesis vendors Verilog HDL Reference Manuals.
【目　录】:
1.0 Lexical Elements
2.0 Registers and Nets
3.0 Compiler Directives
4.0 System Tasks and Functions
5.0 Reserved Keywords
6.0 Structures and Hierarchy
7.0 Expressions and Operators
8.0 Named Blocks, Disabling Blocks
9.0 Tasks and Functions
10.0 Continous Assignments
11.0 Procedural Assignments
12.0 Gate Types, MOS and Bidirectional Switches
13.0 Specify Blocks
14.0 Verilog Synthesis Constructs
15.0 Index