VerilogHDL编写乘法器

hellen

【文件名】:06410@52RD_VerilogHDL编写乘法器.rar
【格　式】:rar
【大　小】:35K
【简　介】:Today’s DSP core vendors are moving to soft cores, in
order to reduce time-to-market and engineering efforts.
One of the critical issues in soft-core design is
implementing a one cycle data throughput fully
synthesizable Multiplier, that fits timing and area goals.
Multiplication timing is a critical design parameter since
in most of the cases the multiplier is located in the critical
path.
【目　录】:无目录