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Lead Physical Design Engineer
• Candidates with greater than three (> 3) years of Experience:
• Experience with one of the major P&R (Place & Route) tool suites (Cadence, Synopsys, Mentor, or Magma).
• Solid background in timing closure and signoff (PrimeTime experience).
• Scripting expertise (Perl, Tcl, or Python) a plus
• Actual chip tapeout experience on a recent technology node (65nm or below) *** preferred ***.
• Strong English communication skills. Both written & oral.
• Prior experience as a team lead, able to assign, and evaluate, and lead small teams of individual contributors.
• Leadership aptitude may be considered as an alternative requirement.
Physical Design Engineer
• Candidates with less than three (< 3) years of Experience:
• Experience with one of the major P&R (Place & Route) tool suites (Cadence, Synopsys, Mentor, or Magma).
• Good understanding of timing closure and signoff (PrimeTime experience preferred).
• Scripting expertise (Perl, Tcl, or Python) a plus
• Understanding of toplevel (SoC) hierarchical design issues.
Location:shanghai
MSN:findhc@hotmail.com |
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