SDRAM的参考设计

Oliverneil

【文件名】:0646@52RD_ref-sdr-sdram-verilog.zip
【格　式】:zip
【大　小】:781K
【简　介】:在Altera网站上找的，因为没钱啦，所以上传一下，富人就资助一下吧，穷人的话上Altera就可以找到。

ref-sdr-sdram-verilog.zip

包括完整说明、TestBench、源程序等，初学者不妨看看，学习一下！

部分介绍：
Introduction
The single data rate (SDR) synchronous dynamic random access memory (SDRAM) controller provides a simplified interface to industry standard SDR SDRAM. The SDR SDRAM Controller is available in either Verilog HDL or VHDL and is optimized for the Altera® APEX™ architecture. The SDR SDRAM Controller supports the following
features:
■ Burst lengths of 1, 2, 4, or 8 data words
■ CAS latency of 2 or 3 clock cycles
■ 16-bit programmable refresh counter used for automatic refresh
■ 2-chip selects for SDRAM devices
■ Supports the NOP, READA, WRITEA, AUTO_REFRESH, PRECHARGE, ACTIVATE, BURST_STOP, and LOAD_MR commands
■ Support for full-page mode operation
■ Data mask line for write operations
■ PLL to increase system performance
■ Support for data-path widths of 16, 32, and 64 bits
【目　录】:无目录

Berry

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