FSM设计的一些指导!

Markmars

【文件名】:0646@52RD_FSM设计指导.rar
【格　式】:rar
【大　小】:222K
【简　介】: FSM is an abbreviation for Finite State Machine.
There are many ways to code FSMs including many very poor ways to code FSMs. This paper will
examine some of the most commonly used FSM coding styles, their advantages and disadvantages, and
offer guidelines for doing efficient coding, simulation and synthesis of FSM designs.
This paper will also detail Accellera SystemVerilog enhancements that will facilitate and enhance future
Verilog FSM designs.
In this paper, multiple references are made to combinational always blocks and sequential always blocks.
Combinational always blocks are always blocks that are used to code combinational logic functionality and
are strictly coded using blocking assignments (see Cummings[4]). A combinational always block has a
combinational sensitivity list, a sensitivity list without "posedge" or "negedge" Verilog keywords.
Sequential always blocks are always blocks that are used to code clocked or sequential logic and are always
coded using nonblocking assignments (see Cummings[4]). A sequential always block has an edge-based
sensitivy list.
【目　录】:
1. Introduction
2. Mealy and Moore FSMs
3. Binary Encoded or Onehot Encoded?
4. FSM Coding Goals
5. Two Always Block FSM Style (Good Style)
6. One Always Block FSM Style (Avoid This Style!)
7. Onehot FSM Coding Style (Good Style)
8. Registered FSM Outputs (Good Style)
9. Comparing RTL Coding Efforts
10. Synthesis Results
11. Running Cadence BuildGates
12. Verilog-2001 Enhancements
13. SystemVerilog Enhancements
14. Conclusions
15. Acknowledgements
16. References