IP Core Design Examples and Documents\IPCore3-Arithmatic-Library

Fredericadil

【文件名】:06331@52RD_arith_lib-1[1].0.zip
【格　式】:zip
【大　小】:247K
【简　介】:再发一个看有人需要不

【目　录】:无目录

Fredericadil

<P>
【文件名】:06331@52RD_IPCore3-Arithmatic-Library.rar
【格　式】:rar
【大　小】:55K
【简　介】:一、Arithmetic units are universal and often performance-critical building blocks on ASICs. Commercial hardware synthesis tools and data path libraries provide efficient circuit generators for the most important  arithmetic operations, starting from a behavioral circuit description e.g. in VHDL. However, the supplie darithmetic units usually lack flexibility for customization, and non-standard arithmetic functions are not
supported.To correct these deficiencies, a library of arithmetic units has been developed in this work. The  requirements for such a library are:

The library contains units for a comprehensive set of arithmetic operations.

The units have multiple structurally different implementations with varying circuit performance,
thus allowing the designer to trade area versus speed.

The units make use of well-performing circuit architectures which are optimized for synthesis and
cell-based design (standard cells, sea-of-gates, fine-grained FPGA)).

The units are made available as circuit generators implemented in parameterized structural and
synthesizable VHDL code. This provides technology (i.e. cell library) and platform (i.e. synthesis
tool) independency as well as simple usage (i.e. by way of component instantiation in a VHDL
circuit description).

The units are implemented in a flexible and modular way in order to enable easy customization.
This also calls for well-documented source code.</P>
<P>二、Arithmetic units are universal and often performance-critical building blocks on ASICs. Commercial
hardware synthesis tools and data path libraries provide efficient circuit generators for the most important
arithmetic operations, starting from a behavioral circuit description e.g. in VHDL. However, the supplied
arithmetic units usually lack flexibility for customization, and non-standard arithmetic functions are not
supported.
To correct these deficiencies, a library of arithmetic units has been developed in this work. The
requirements for such a library are:

The library contains units for a comprehensive set of arithmetic operations.

The units have multiple structurally different implementations with varying circuit performance,
thus allowing the designer to trade area versus speed.

The units make use of well-performing circuit architectures which are optimized for synthesis and
cell-based design (standard cells, sea-of-gates, fine-grained FPGA).

The units are made available as circuit generators implemented in parameterized structural and
synthesizable VHDL code. This provides technology (i.e. cell library) and platform (i.e. synthesis
tool) independency as well as simple usage (i.e. by way of component instantiation in a VHDL
circuit description).
【目　录】:
一、1 .Introduction
       2 .Foundations
       3 .Implementation
       4 .Conclusions
       5.References</P>
<P>二、1. Introduction</P>
<P>       2 .Foundations</P>
<P>       3 .Implementation</P>
<P>       4. Conclusions</P>
<P>       5.References


</P>