初学者的关于Testbench的文章

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【简　介】:Due to increases in design size and complexity, digital design verification has become an
increasingly difficult and laborious task. To meet this challenge, verification engineers rely on
several verification tools and methods. For large, multi-million gate designs, engineers typically
use a suite of formal verification tools. However, for smaller designs, design engineers usually
find that HDL simulators with testbenches work best.
Testbenches have become the standard method to verify HLL (High-Level Language) designs.
Typically, testbenches perform the following tasks:
• Instantiate the design under test (DUT)
• Stimulate the DUT by applying test vectors to the model
• Output results to a terminal or waveform window for visual inspection
• Optionally compare actual results to expected results
Typically, testbenches are written in the industry-standard VHDL or Verilog hardware
description languages. Testbenches invoke the functional design, then stimulate it. Complex
testbenches perform additional functions—for example, they contain logic to determine the
proper design stimulus for the design or to compare actual to expected results.
The remaining sections of this note describe the structure of a well-composed testbench, and
provide an example of a self-checking testbench—one that automates the comparison of actual
to expected testbench results.
Figure 1 shows a standard HDL verification flow which follows the steps outlined above.
Since testbenches are written in VHDL or Verilog, testbench verification flows can be ported
across platforms and vendor tools. Also, since VHDL and Verilog are standard non-proprietary
【目　录】:
1.Generating Clock Signals
2.Providing Stimulus
3.Displaying Results
4.Configuration Statement (VHDL)
5.Initializing Block RAMs for Simulation
6.Breaking Up Stimulus Blocks with Tasks and Procedures
7.Controlling Bidirectional Signals in Simulation
8.Initializing Memory for Simulation