quartusII学习资料

aaronno

【文件名】:06330@52RD_quartusII学习资料[1].part1.rar
【格　式】:rar
【大　小】:1807K
【简　介】:  
一、Quartus Development System features:
–Fully integrated design entry, processing, and verification tools:
•Multiple design entry methods
•Logic synthesis
•Place & route
•Simulation
•Timing analysis
•Device programming
–NativeLink
–Revision Control Interface
–Intellectual Property (IP) Support
–SignalTap
–Extensive On-Line Help
二、Compiler Settings and Focus Points
–Introduction
nCompiler Settings Wizard
nCompilation Steps
nCompiler Settings Menu
–Edit existing compiler settings
–Non-Wizard settings
nCompiler Settings File (.CSF)
nCompiler Report
nSummary
三、 Quartus is capable of doing single clock design timing analysis and multi-clock design timing analysis
nSingle clock timing analysis
–Fmax (maximum clocking frequency)
–Tsu, Th, Tco (setup time, hold time, clock-to-out time)
–Slack analysis for Fmax (incl. delays to/from pins)
nMulti-clock analysis
–Allows user to analyze timing for a design containing register-to-register paths which are controlled by different clocks
–Slack analysis is used
nCombinatorial Loop Detection
–Quartus automatically detects combinatorial loops
四、Simulator
–Features
–Supported simulation methods
–3rd party simulators
nSimulator settings
–Simulation Modes
–End Time
–Options
–Simulation Focus
–Saving Simulator Settings

【目　录】:
一、1.Designing with Quartus
2.Quartus Development System Feature Overview
3.Quartus Development System
4.More Features
5.Quartus Operating Environment
6.Quartus Design Methodology
二、 1.Quartus Compilation
  2.Agenda
  3.Controlling Synthesis & Fitting
4. What are Compiler Settings?
5.What are Focus Points?
6.Benefit of Compiler Settings
三、1.Timing Analysis in Quartus
2.Features
3.In This Section
4.Compile Design
四、1.Quartus Simulator
       2.In This Section
       3.In This Section Continued
       4. Simulator

aaronno

【文件名】:06330@52RD_quartusII学习资料[1].part2.rar
【格　式】:rar
【大　小】:849K
【简　介】:
【目　录】: