讨论下PLL的CSR/CSP

darwin18

据资料称，Cycle slip reduction(CSR)或Cycle Slip Prevention（CSP）能减少PLL的锁定时间。
但是小弟的实际测试结果并没有明显的效果，使用该功能有什么需要特别注意的吗?
请高手指点一下。

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资料：
When the Vco is not yet locked to the reference, the instantaneous frequencies of the two paths are different, and
the phase difference of the two paths at the PfD varies rapidly over a range much greater than ±2π radians. since
the gain of the PfD varies linearly with phase up to ±2π, the gain of a conventional PfD will cycle from high gain,
when the phase difference approaches a multiple of 2π, to low gain, when the phase difference is slightly larger than
a multiple of 0 radians. the charge on the loop filter small cap may actually discharge slightly during the low gain
portion of the cycle. this can make the Vco frequency actually reverse temporarily during locking. this phenomena
is known as cycle slipping. cycle slipping causes the pull-in rate during the locking phase to vary cyclically as shown
in the red curve in figure, and increases the time to lock to a value far greater than that predicted by normal small
signal Laplace analysis.
<img src="attachments/dvbbs/2010-5/20105822491173499.jpg" border="0" onclick="zoom(this)" onload="if(this.width>document.body.clientWidth*0.5) {this.resized=true;this.width=document.body.clientWidth*0.5;this.style.cursor='pointer';} else {this.onclick=null}" alt="" />

darwin18

顶一下，别沉了。