再给大家共享一个I2C与存储器的IP

diandian1

【文件名】:06319@52RD_再给大家共享一个I2C与存储器的IP.rar
【格　式】:rar
【大　小】:205K
【简　介】:The I
2
C bus provides a simple two-wire means of communication. This protocol is used in many applications.
SDRAM modules implement a serial EEPROM that supports the I
2
C protocol. This is used so that a microprocessor
can read the EEPROM for configuration purposes.
This reference design documents an I
2
C Controller designed to interface with serial EEPROM devices. It is
intended to be a simple controller providing random reads cycles only. Typically, serial EEPROMs are programmed
at board assembly time and store configuration information, which is read by a microprocessor during power-up.
This design was implemented in Verilog, synthesized and fitted using Lattice’s ispDesignEXPERT™ software into a
ispMACH™ 4A device. The design requires 46 macrocells and 24 I/O pins. Using an M4A-64/32-55 yields greater
than 153MHz performance. Results may vary according to the synthesis tool.
This design assumes the user has experience with I
2
C controllers. Information available in documents listed in the
Applicable Documents section, below, is not repeated in this document.
【目　录】:
Introduction.
Applicable Documents
Theory of Operation
Test Bench Description
Design Flow
Timing Diagrams

mnlhd

<b>共享!=免费</b>