物有所值 高通6010．6020.6030 datasheet

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1.1 Documentation overview...................................................................................... 15
1.2 Concise device and application descriptions........................................................ 17
1.2.1 Analog/RF functional description........................................................ 20
1.2.2 Baseband functional description .......................................................... 21
1.2.3 Power management functional description .......................................... 22
1.2.4 QSC60X0 variants ............................................................................... 23
1.3 Terms and acronyms............................................................................................. 24
1.4 Special marks ....................................................................................................... 26
2 Pin Definitions
2.1 Pin assignments .................................................................................................... 29
2.2 Pin descriptions .................................................................................................... 30
3 RF Signal Paths and LO Circuits
3.1 RF receive signal path .......................................................................................... 43
3.1.1 RF receiver features ............................................................................. 44
3.1.2 RF receiver connections....................................................................... 44
3.2 Rx LO circuits ...................................................................................................... 46
3.2.1 Rx LO features ..................................................................................... 47
3.2.2 Rx LO connections .............................................................................. 47
3.3 RF transmit signal path......................................................................................... 48
3.3.1 RF transmitter features......................................................................... 49
3.3.2 RF transmitter connections .................................................................. 49
3.4 Tx LO circuits ...................................................................................................... 51
3.4.1 Tx LO features ..................................................................................... 51
3.4.2 Tx LO connections............................................................................... 51
4 Audio and Housekeeping ADC
4.1 Audio .................................................................................................................... 52
4.1.1 Audio connections ............................................................................... 53
4.1.2 Tx path inputs and gains ...................................................................... 54
4.1.3 Rx path outputs .................................................................................... 55
4.1.4 Side-tone path ...................................................................................... 55
4.1.5 Audio DSP ........................................................................................... 55
4.1.6 Recommended gain settings ................................................................ 57
Contents
80-VA552-3 Rev. A 3 QUALCOMM Proprietary
QSC60X0™ QUALCOMM Single Chip™ User Guide Contents
4.1.7 PCM interface ...................................................................................... 58
4.1.8 External analog interface details .......................................................... 61
4.2 Housekeeping ADC.............................................................................................. 64
4.2.1 HKADC connections ........................................................................... 65
4.2.2 Analog input voltage range .................................................................. 65
4.2.3 HKADC operation (including conversion time).................................. 65
4.2.4 HKADC analog interface considerations............................................. 66
4.2.5 Example HKADC application: temperature sensor ............................. 67
5 Baseband Processors
5.1 Modem subsystem................................................................................................ 70
5.1.1 Advanced high-performance bus system ............................................. 71
5.1.2 Modem microprocessor - ARM926EJ-S ............................................. 71
5.1.3 Memory map and memory map decoder ............................................. 73
5.1.4 Reset and pause.................................................................................... 75
5.1.5 Watchdog timer .................................................................................... 78
5.1.6 mDSP ................................................................................................... 78
5.2 Application subsystem ......................................................................................... 78
5.2.1 aDSP .................................................................................................... 78
6 Memory Support
6.1 Single EBI mode (QSC6010 only)....................................................................... 80
6.1.1 Single EBI connections........................................................................ 80
6.1.2 Single EBI memory support................................................................. 84
6.1.3 Single EBI memory configurations...................................................... 85
6.1.4 Single EBI chip select configuration ................................................... 86
6.2 Dual EBI mode (QSC6020 and QSC6030 only).................................................. 87
6.2.1 Dual EBI memory support ................................................................... 87
6.2.2 Dual EBI memory configuration.......................................................... 88
6.2.3 Dual EBI chip select configuration...................................................... 89
6.3 EBI I/O timing...................................................................................................... 90
6.3.1 EBI timing features .............................................................................. 90
6.3.2 I/O clock............................................................................................... 90
6.3.3 Adaptive timing.................................................................................... 91
6.3.4 Adaptive timing software setting ......................................................... 91
6.4 EBI1...................................................................................................................... 93
6.4.1 EBI1 features ....................................................................................... 93
6.4.2 EBI1 connections ................................................................................. 94
6.4.3 EBI1 memory support.......................................................................... 95
6.5 EBI2...................................................................................................................... 96
6.5.1 EBI2 features ....................................................................................... 96
6.5.2 EBI2 connections ................................................................................. 97
6.5.3 EBI2 memory support.......................................................................... 98
6.5.4 EBI2 chip select configuration............................................................. 99
80-VA552-3 Rev. A 4 QUALCOMM Proprietary
QSC60X0™ QUALCOMM Single Chip™ User Guide Contents
6.6 Boot-up specification ......................................................................................... 100
6.6.1 Using the BUSY_N pin...................................................................... 100
6.7 External memory controller features.................................................................. 101
6.7.1 Burst memory controller features ...................................................... 101
6.7.2 Asynchronous memory controller features ........................................ 102
6.7.3 Page memory controller features ....................................................... 102
6.7.4 LCD device controller features (through EBI2 controller) ................ 102
6.8 EBI operating modes and parameters................................................................. 103
6.8.1 INIT_LATENCY and WAIT cycles................................................... 103
6.8.2 HOLD cycles...................................................................................... 104
6.8.3 Recovery cycles ................................................................................. 104
6.8.4 Write precharge (WR_PRECHARGE) cycles ................................... 105
6.8.5 Page size............................................................................................. 106
6.8.6 Page read ............................................................................................ 106
6.8.7 Page memory initialization ................................................................ 106
6.8.8 Synchronous burst memory ............................................................... 107
6.8.9 Burst memory initialization ............................................................... 107
6.8.10 WRAP8 READ/INCR burst optimization ......................................... 110
6.8.11 Burst memory program...................................................................... 111
6.8.12 Precharge cycles................................................................................. 112
6.8.13 WRAP8_RD_MODE = 1 .................................................................. 114
6.8.14 WRAP8_RD_MODE = 0 .................................................................. 114
6.8.15 ADV_OE_RECOVERY..................................................................... 114
6.8.16 ADDR_HOLD_ENA......................................................................... 115
6.8.17 WE_TIMING..................................................................................... 115
6.8.18 IGN_WAIT_FOR_WR ...................................................................... 115
6.8.19 IGN_WAIT_FOR_RD ....................................................................... 116
6.8.20 PWRSAVE_MODE feature ............................................................... 116
6.8.21 Low power mode control using UXMC_PSRAM_CRE_CFG ......... 116
6.9 LCD interface ..................................................................................................... 117
6.9.1 LCD_RS support................................................................................ 117
6.9.2 LCD_EN support ............................................................................... 118
6.9.3 LCD_RECOVERY ............................................................................ 118
6.9.4 LCD HOLD cycles............................................................................. 118
6.9.5 LCD WAIT cycles.............................................................................. 119
6.9.6 LCD_BYTE_DEVICE_ENA ............................................................ 119
6.10 NAND controller ................................................................................................ 119
6.10.1 NAND controller architecture............................................................ 120
6.10.2 Support for two NAND flash devices ................................................ 121
6.10.3 ECC for NAND 8-bit interface .......................................................... 121
80-VA552-3 Rev. A 5 QUALCOMM Proprietary
QSC60X0™ QUALCOMM Single Chip™ User Guide Contents
7 Air Interfaces
7.1 CDMA air interfaces .......................................................................................... 124
8 Camera Interface and Video (QSC6030 device only)
8.1 CAMIF features.................................................................................................. 127
8.2 CAMIF connections ........................................................................................... 127
8.3 CAMIF clock requirements................................................................................ 131
8.4 CAMIF synchronization capabilities.................................................................. 132
8.4.1 Active physical synchronization ........................................................ 132
8.4.2 Embedded synchronization................................................................ 132
8.5 Frame synchronization and windowing.............................................................. 134
8.6 Subsampling support .......................................................................................... 136
8.7 CAMIF timing requirements .............................................................................. 137
8.8 Integrated JPEG encoder .................................................................................... 138
9 Connectivity
9.1 Keypad interface................................................................................................. 139
9.1.1 Keypad features.................................................................................. 140
9.1.2 Keypad connections ........................................................................... 141
9.2 UARTs................................................................................................................ 142
9.2.1 UART features ................................................................................... 143
9.2.2 UART connections............................................................................. 143
9.2.3 UART transmitter............................................................................... 145
9.2.4 UART receiver ................................................................................... 146
9.2.5 UART clock source ............................................................................ 147
9.2.6 UART bit rate generator..................................................................... 148
9.2.7 UART interrupts................................................................................. 148
9.2.8 IrDA interface .................................................................................... 149
9.3 RUIM.................................................................................................................. 150
9.3.1 RUIM features.................................................................................... 150
9.3.2 RUIM connections ............................................................................. 150
9.3.3 RUIM setup........................................................................................ 151
9.3.4 Selecting an RUIM clock source........................................................ 152
9.3.5 RUIM boost option ............................................................................ 152
9.3.6 RUIM/SIM software implementation ................................................ 152
9.4 Ringer ................................................................................................................. 154
9.4.1 External ringer booster circuit ........................................................... 156
9.5 I2C Interface....................................................................................................... 157
9.5.1 I2C features ........................................................................................ 158
9.5.2 I2C connections ................................................................................. 158

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