80-VA736-2 MSM7200 Software Interface

Kajros

【文件名】:09420@52RD_80-VA736-2-MSM7200-SoftwareInterface.rar
【格　式】:rar
【大　小】:2672K
【简　介】:
【目　录】:
1 Clocks Registers
1.1 Introduction .......................................................................................................... 14
1.2 ARM registers ...................................................................................................... 14
1.2.1 Clock register definitions ..................................................................... 14
1.2.2 Power register definitions .................................................................... 95
2 Security Registers
2.1 MPU registers..................................................................................................... 108
2.2 Security mode control module registers............................................................. 116
3 Crypto Engine Registers
3.1 ARM registers .................................................................................................... 124
3.1.1 Crypto engine registers ...................................................................... 124
3.2 Crypto engine operation ..................................................................................... 132
3.2.1 Packet segment................................................................................... 133
3.2.2 Supplying/retrieving segment data .................................................... 133
3.2.3 Working with hash engine ................................................................. 134
3.2.4 Working with context ........................................................................ 134
3.2.5 Counter mode..................................................................................... 135
3.2.6 Clearing residual context and state .................................................... 135
3.2.7 Software debug assist - CE error ....................................................... 135
4 AXI Bus Registers
4.1 Overview ............................................................................................................ 137
4.2 AXI EBI1 global interconnect registers ............................................................. 137
4.2.1 Introduction........................................................................................ 137
4.2.2 ARM registers.................................................................................... 137
Peripheral Bus Registers
5.1 ARM registers .................................................................................................... 166
5.1.1 Configuration registers....................................................................... 166
5.1.2 Bus error registers .............................................................................. 171
5.1.3 Peripheral Bus MPU Registers .......................................................... 175
6 Peripheral Web Registers
6.1 SyncPerphWeb (SPWB) registers ...................................................................... 180
6.1.1 Codec SSBI registers ......................................................................... 180
6.1.2 TSSC and miscellaneous registers ..................................................... 183
6.1.3 Register programming guidelines ...................................................... 196
6.1.4 Notes on CODEC_SSBI_CTL register.............................................. 197
7 EBI1 Registers
7.1 Register data ....................................................................................................... 199
7.2 ARM registers .................................................................................................... 199
8 AsyncPerphWeb (APWB) registers
8.1 Aux and WB CODEC registers.......................................................................... 235
8.1.1 I2C registers ....................................................................................... 237
8.1.2 Misc registers ..................................................................................... 240
8.1.3 Register programming guidelines ...................................................... 243
9 SMI Registers
9.1 SMI Registers ..................................................................................................... 247
10 EBI2 Registers
10.1 ARM registers .................................................................................................... 283
10.2 EBI2 NAND controller registers........................................................................ 295
10.2.1 MPU registers .................................................................................... 349
11 NAND Controller Software Interface
11.1 MPU registers..................................................................................................... 411
12 Data Mover Registers
12.1 ARM registers .................................................................................................... 420
12.1.1 Host Interface 0 Security Domain 0................................................... 420
12.1.2 Host Interface 0 Security Domain 1................................................... 430
12.1.3 Host Interface 0 Security Domain 2................................................... 435
12.1.4 Host Interface 0 Security Domain 3................................................... 440
13 Modem Subsystem Registers
13.1 MSS AHB registers ............................................................................................ 445
13.1.1 ARM registers.................................................................................... 445
Integrity Algorithm
14.1 ARM registers .................................................................................................... 451
15 Modem Clocks
15.1 ARM registers .................................................................................................... 455
15.1.1 Standard clock control registers......................................................... 455
15.1.2 MDSP clock control (ARM-governed).............................................. 485
16 Modem Web
16.1 ARM registers .................................................................................................... 489
17 Modem Power Manager
17.1 ARM Registers................................................................................................... 504
17.1.1 Clock registers ................................................................................... 505
17.1.2 Sleep timer registers........................................................................... 506
17.1.3 Power controller registers .................................................................. 507
17.1.4 Interrupt controller registers .............................................................. 509
17.1.5 Debug registers .................................................................................. 517
17.1.6 JTAG state register ............................................................................ 518
17.1.7 Touch screen debounce registers ....................................................... 519
17.1.8 Control for EBI bus freeze during warm boot ................................... 520
17.1.9 Regfile registers ................................................................................. 520
18 MSS_HDLC
18.0.1 ARM registers.................................................................................... 521
19 Modem Subsystem Interrupt Controller
19.1 Introduction ........................................................................................................ 528
19.2 Interrupt map ...................................................................................................... 528
19.3 ARM registers .................................................................................................... 530
19.3.1 Interrupt controller write registers ..................................................... 531
19.3.2 Interrupt controller read/write registers ............................................. 537
19.3.3 Interrupt controller read registers....................................................... 542
19.3.4 Control for Edge / Level Sensitivity .................................................. 547
19.3.5 Secondary interrupt control registers ................................................. 550
19.3.6 Priority interrupt controller registers ................................................. 564
19.3.7 Inter-processor communication registers ........................................... 565
20 MSS Miscellaneous Registers
20.0.1 Misc chip control ............................................................................... 568
20.0.2 Modem ARM debug .......................................................................... 569
21 ARM11 Subsystem Peripheral Registers
21.1 ARM11 VIC and private peripheral AHB registers........................................... 571
21.2 ACC_AHBP_CLK registers............................................................................... 572
21.2.1 VIC registers ...................................................................................... 572
22 MDP Registers
22.1 ARM registers .................................................................................................... 596
22.1.1 Synchronization registers................................................................... 596
22.1.2 Interrupt registers ............................................................................... 600
22.1.3 Operation control registers................................................................. 602
22.2 Debug access ...................................................................................................... 635
22.2.1 Test pattern registers .......................................................................... 636
22.2.2 Test mode registers ............................................................................ 636
23 TV_ENC Registers
23.1 Introduction ........................................................................................................ 637
23.2 ARM registers .................................................................................................... 637
24 UART and UART1DM Registers
24.1 UART registers................................................................................................... 648
24.1.1 ARM registers.................................................................................... 648
24.2 UART1DM......................................................................................................... 687
24.2.1 ARM registers.................................................................................... 687
25 TLMM and GPIO Registers
25.1 Overview ............................................................................................................ 704
25.2 GPIO1 registers .................................................................................................. 705
25.2.1 Overview............................................................................................ 705
25.2.2 GPIO1 output value registers............................................................. 707
25.2.3 GPIO1 output enabling registers........................................................ 708
25.2.4 GPIO1 alternate function registers..................................................... 709
25.2.5 GPIO1 input value registers............................................................... 721
25.2.6 GPIO1 interrupt controller registers .................................................. 722
25.2.7 GPIO security control registers.......................................................... 727
25.2.8 TOPMUX registers ............................................................................ 728
25.3 GPIO2 registers .................................................................................................. 742
25.3.1 GPIO2 output value register .............................................................. 742
25.3.2 GPIO2 output enabling register ......................................................... 742
25.3.3 GPIO2 alternate function registers..................................................... 742
25.3.4 GPIO2 input value registers............................................................... 747
25.3.5 GPIO2 interrupt controller registers .................................................. 747
25.3.6 GPIO2 security control registers........................................................ 749
25.4 GPIO1 shadow registers..................................................................................... 749
25.4.1 GPIOSH1 output value registers........................................................ 750
25.4.2 GPIOSH1 output enabling registers................................................... 751
25.4.3 GPIOSH1 input value registers.......................................................... 752
25.4.4 GPIOSH1 interrupt controller registers ............................................. 753
GPIO2 shadow registers..................................................................................... 757
25.5.1 GPIOSH2 output value register ......................................................... 758
25.5.2 GPIOSH2 output enabling register .................................................... 758
25.5.3 GPIOSH2 input value registers.......................................................... 758
25.5.4 GPIOSH2 interrupt controller registers ............................................. 759
26 Efuse Registers
26.1 Efuse registers .................................................................................................... 761
26.2 Notes on FEC and blowing fuses ....................................................................... 764
26.3 The ALL_DEBUG_DISABLE fuse................................................................... 764
27 MDDI Camera Interface Registers
27.1 ARM registers .................................................................................................... 765
27.1.1 MDDI CAMIF control registers ........................................................ 765
27.1.2 MDDI CAMIF self-test registers ....................................................... 768
27.1.3 MDDI client configuration registers .................................................. 769
27.1.4 MDDI client pad configuration registers ........................................... 770
27.1.5 MDDI CAMIF video buffer read and write registers ........................ 773
27.1.6 MDDI CAMIF reverse link encapsulation registers .......................... 775
27.1.7 MDDI CAMIF forward link registers................................................ 777
27.1.8 Test MISR software registers............................................................. 778
28 IMEM Registers
28.1 ARM Registers................................................................................................... 783
28.2 Configuration Register ....................................................................................... 783
29 Mobile Display Digital Interface
29.1 Introduction ........................................................................................................ 785
29.2 ARM registers .................................................................................................... 785
29.2.1 MDDI read/write registers ................................................................. 785
30 Secure Digital Card Controller Registers
30.1 Introduction ........................................................................................................ 797
30.2 ARM registers .................................................................................................... 797
31 TSIF Registers
31.1 TSIF registers ..................................................................................................... 808
31.1.1 TSIF status and control ...................................................................... 808
31.1.2 TSIF time limit................................................................................... 810
31.1.3 TSIF clock reference (TCR) counter ................................................. 810
31.1.4 TSIF loop back flags .......................................................................... 811
31.1.5 TSIF loop back data ........................................................................... 811
31.1.6 Test bus control.................................................................................. 812
31.1.7 TSIF MISR TEST MODE ................................................................. 812
31.1.8 MISR TEST MISR RESET ............................................................... 812
31.1.9 TSIF TEST EXPORT MISR ............................................................. 813
31.1.10 TSIF TEST MISR CURR VAL......................................................... 813
31.1.11 TSIF data port .................................................................................... 814
31.2 TSIF Software Sequences .................................................................................. 814
31.2.1 Normal Operation .............................................................................. 814
31.2.2 Loop Back Operation Without Errors................................................ 814
31.2.3 Loop Back Operation With Errors..................................................... 815
32 USB_OTG Registers
32.1 Introduction ........................................................................................................ 816
32.2 ARM registers .................................................................................................... 816
32.2.1 Glue logic registers ............................................................................ 816
32.2.2 Core-level registers ............................................................................ 823
32.2.3 Host registers ..................................................................................... 836
32.2.4 Function registers............................................................................... 846
32.2.5 DMA registers.................................................................................... 863
32.3 TDI programmable USB core registers.............................................................. 869
32.3.1 Host endpoint transfer descriptor format ........................................... 869
32.3.2 Function endpoint descriptor format.................................................. 878
33 CODEC and Touch Screen HKADC
33.1 CODEC registers................................................................................................ 882
33.2 Touch Screen ADC registers.............................................................................. 905

haogo

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foxlx

谢谢楼主分享。

zhangziying

发的啥玩意啊。一点用都没有

ytian37

非常好的资料,谢谢楼主!

pic2

谢谢楼主

EverestDH

nice work!!
thank you for your sharing!!

cerberus

不错不错

uus169

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kerwin

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boodboy2010

谢谢楼主共享

lizidong110

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