Very good RTL coding style guide

zlhlsy

分享点实用的东西
【文件名】:09214@52RD_RTL Design Style Guide for Verilog - V1.0 - Chapter 1.pdf
【格　式】:pdf
【大　小】:2038K
【简　介】: This chapter introduces naming conventions and synchronous design issues that should be kept in mind during the design process, as well as considerations and cautions relating to asynchronous design, clocks, and hierarchical design.
【目　录】: 1.1 Naming conventions
1.2 Synchronous design
1.3 Initial reset
1.4 Clocks
1.5 Handling of asynchronous circuits
1.6 Hierarchical design

zlhlsy

【文件名】:09214@52RD_RTL Design Style Guide for Verilog - V1.0 - Chapter 2.pdf
【格　式】:pdf
【大　小】:1718K
【简　介】:This chapter introduces the basic style of RTL description using Verilog-HDL. In addition, it discusses items of which to take note when coding and provides some example codes. Performance of the synthesized circuits and the readability of the source code can be improved by following the description style and cautionary items introduced in this chapter.
【目　录】:2.1 Combinational logic
2.2 always construct description in combinational logic
2.3 FF inference
2.4 Latch inference
2.5 Tri-state buffer
2.6 always construct description that takes circuit structure into account
2.7 if statements
2.8 case statements
2.9 for statements
2.10 Operator descriptions
2.11 State machine descriptions

zlhlsy

【文件名】:09214@52RD_RTL Design Style Guide for Verilog - V1.0 - Chapter 3.pdf
【格　式】:pdf
【大　小】:2740K
【简　介】:This chapter introduces the methodology for creating function libraries, the parameterization of design resources, test facilitation design, low power consumption design, and methods for managing design data. This chapter also introduces the methodology for improving design quality and the reusability of design resources.
【目　录】:3.1 Create function libraries
3.2 Using function libraries
3.3 Design for Test (DFT)
3.4 Low Power-Consumption Design
3.5 Source codes and design data management

peaking1981

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