Digital Frequency Synthesis Demystified

neil1981

数字频率合成器
【文件名】:0637@52RD_Digital Frequency Synthesis Demystified.rar
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【目　录】:
Chapter 1. Introduction to Frequency Synthesis 1
1-1 Introduction and Definitions 1
1-2 Synthesizer Parameters 5
1-2-1 Frequency Range 6
1-2-2 Frequency Resolution 6
1-2-3 Output Level 7
1-2-4 Control and Interface 7
1-2-5 Output Flatness 7
1-2-6 Output Impedance 7
1-2-7 Switching Speed 7
1-2-8 Phase Transient 8
1-2-9 Harmonics 9
1-2-10 Spurious Output 10
1-2-11 Phase Noise 10
1-2-12 Standard Reference 13
1-3 Auxiliary Specifications 13
1-4 Review of Synthesis Techniques 13
1-4-1 Phase-Locked Loop 14
1-4-2 Direct Analog Synthesis 21
1-4-3 Direct Digital Synthesis 26
1-5 Comparative Analysis 35
1-6 Conclusion 37
References 38
Chapter 2. Frequency Synthesizer System Analysis 39
2-1 Multiplying and Dividing 39
2-2 Phase Noise 42
2-3 Spurious and Phase Noise in PLL 49
2-4 Phase Noise Mechanism 51
2-4-1 Noise in Dividers 51
2-4-2 Noise in Oscillators 51
2-4-3 Noise in Phase Detectors 52
2-5 Mixing and Filtering 53
2-6 Frequency Planning 55
Chapter 3. Measurement Techniques 57
3-1 Switching Speed 57
3-2 Phase Noise 61
3-2-1 FM Noise 62
3-2-2 Delay Line Discriminator 63
3-2-3 Integrated Phase Noise 66
3-2-4 Noise Density 66
3-3 Phase Continuity 66
3-4 Spurious Signals (Especially DDS) 67
3-5 Phase Memory 69
3-6 Step Size 69
3-7 Linear FM 70
3-8 Conclusion 70
References 71
Chapter 4. DDS General Architecture 73
4-1 Digital Modulators and Signal Reconstruction 75
4-2 Pulse Output DDS of the First Order 82
4-3 Pulse Output DDS of the Second Order 87
4-4 Standard DDS 89
4-4-1 Binary-Coded Decimal DDS 100
4-5 Randomization 105
4-5-1 Wheatley Procedure 106
4-5-2 Randomizing Sine Output 108
4-6 Quantization Errors 109
4-6-1 Digitized Model 109
4-7 Logic Speed Considerations 120
4-8 Modulation 120
4-9 State-of-the-Art Components and Systems 128
4-9-1 Very High-Speed Direct Digital Synthesizer 128
4-9-2 Medium-Speed Direct Digital Synthesizer 129
4-10 Performance Evaluation 133
4-10-1 Switching Speed 133
4-10-2 Phase Noise 133
4-10-3 Spurious Signals 134
4-10-4 Phase Continuity 134
4-10-5 Resolution 134
4-11 Sample-and-Hold Devices 134
4-12 Single-Bit DDS Revisited 135
4-13 Arbitrary Waveform Generators
Chapter 5. Phase-Locked Loop Synthesizers
5-1 Main Components of PLL Synthesis
5-1-1 Voltage Controlled Oscillators
5-1-2 Analog Phase Detector
5-1-3 Digital Phase Detector 1
5-1-4 Digital Phase Detector 2
5-1-5 Digital Phase Detector 3
5-1-6 Digital/Analog Phase Detector 4
5-1-7 Dividers
5-2 Performance Evaluation
5-2-1 Wireless PLL ASIC Configuration
5-3 Fractional-N Synthesizers
5-3-1 Fractional-N Synthesis of the First Order
5-3-2 Fractional-N Synthesis of the Second Order
5-4 Fractional-N Synthesis of the Third Order
5-5 DDS-Based PLL
5-5-1 Speed Up
5-6 Single-Chip PLL Synthesis
5-7 Conclusion
References
Chapter 6. Accumulators
6-1 Binary Accumulators
6-2 Decimal Accumulators
6-3 Interface to ROM
6-4 Accumulator DDS
6-5 Phase Adder and Accumulator Segmentation
6-6 Conclusion
References
Chapter 7. Lookup Table and Sine ROM Compression
7-1 ROM Algorithm
7-2 Quadrant Compression
7-3 Compression Principles
7-4 Direct Taylor Approximation
7-5 Hutchison Algorithm
7-6 Sunderland Algorithm
7-7 Variations and Randomization
7-8 Auxiliary Function ROM Approximation
7-8-1 Spurious Signal Analysis