Verilog Coding Style for Efficient Digital Design

jianli8

【文件名】:06228@52RD_Verilog Coding Style For Efficient Digital Design.rar
【格　式】:rar
【大　小】:80K
【简　介】:
Abstract: In this paper, we discuss efficient coding and design styles using verilog. This can be
immensely helpful for any digital designer initiating designs. Here, we address different problems ranging
from RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All these
problems are accompanied by an example to have a better idea, and these can be taken care off if these
coding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,
here we try to cover a few of them.
【目　录】:6 pages

clyde

<P>This could be download freely.</P>Here.