EMI Design Guidelines for USB Components Intel的文章

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【文件名】:06227@52RD_EMI Design Guidelines for USB Components.pdf
【格　式】:pdf
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1. Disclaimer
This document is provided "as is" with no warranties whatsoever, including any warranty of
merchantability, fitness for any particular purpose, or any warranty otherwise arising out of proposal,
specification, or sample. No license, express or implied, by estoppel or otherwise, to any other intellectual
property rights is granted herein. Intel disclaims all liability, including liability for infringement of any
proprietary rights, relating to implementation of information in this document.
2. Introduction
These developers notes describe electrical and mechanical guidelines for the design of EMC compatible
USB devices. A description of EMI test procedures is given, followed by a brief review of the theory
behind EMI phenomena. Design guidelines for electrical, PC layout and mechanical considerations are
then presented for low and full speed devices, USB cables, and hubs.
【目　录】:

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Draft 13
7. Appendix 1: USB Device EMI Checklists
7.1 Checklist for USB Hosts
7.1.1 Edge Rates
EMI 1 Does the host have per-port edge rate control? yes___ no___
EMI 2 Do ports that are enumerate as low speed shut off full speed downstream
signaling?
yes___ no___
EMI 3 Are full speed signaling edge rates between 4.0 and 20.0 ns? yes___ no___
EMI 4 Are low speed signaling edge rates between 75 and 300 ns? yes___ no___
EMI 5 Does a hub’s upstream port signal at full speed edge rates (4.0 - 20.0 ns) for
all traffic?
yes___ no___
EMI 6 Do the D+ and D- lines have 47 pf termination capacitors yes___ no___
7.1.2 Electrical
EMI 7 Are the VBUS and Gnd lines bypassed with ferrite beads? yes___ no___
EMI 8 Are the D+ and D- lines bypassed with ferrite beads? yes___ no___
EMI 9 Are the ferrite beads placed as close as possible to the USB connector? yes___ no___
EMI 10 Do D+ and D- have series termination resistors such that Z DRIVER + ZTERM =
45W?
yes___ no___
EMI 11 Are the series resistors located as close to the driver chip as is possible? yes___ no___
EMI 12 Is the D+ and D- PC trace impedance 90W +/- 15% yes___ no___
EMI 13 Are the D+ and D- traces routed so that they are not running near to any traces
carrying high speed signals, such as clocks?
yes___ no___
EMI 14 Are the D+ and D- traces routed parallel to each other yes___ no___
EMI 15 Do the D+ and D- traces have grounded guard traces around them yes___ no___
EMI 16 Are the USB output driver VCC pins bypassed with dedicated capacitor(s) yes___ no___
EMI 17 Are there termination capacitors on D+ and D- to Gnd? These are optional but
are effective in limiting emissions.
yes___ no___
EMI 18 Are the termination capacitors located between the USB driver chip and the
series termination resistors?
yes___ no___ na___
EMI 19 Does USB VBUS have a .01mf bypass capacitor to Gnd? yes___ no___
EMI 20 Is this capacitor connected to Gnd as close to the chassis as possible yes___ no___
7.1.3 USB Driver Chip Layout
EMI 21 Are D+ and D- placed such that there are no adjacent pins carrying high speed
signals?
yes___ no___
EMI 22 Does the VCC supplying the USB output drivers have one or more dedicated
power pins?
yes___ no___
EMI 23 Does the Gnd supplying the USB output drivers have one or more dedicated
power pins?
yes___ no___
EMI 24 Do the USB drivers have the necessary number of VCC and Gnd pins to handle
~40 ma for each pair of D+ and D- pins?
yes___ no___
EMI 25 Does the USB driver chip use as low frequency a clock as is feasible? yes___ no___ na___
7.1.4 USB Receptacles
EMI 26 Are the USB receptacles located away from other high speed circuitry or
traces?
yes___ no___
EMI 27 Does the USB receptacle shell make multiple low impedance connections to
the motherboard ground plane?
yes___ no___
Draft 14
EMI 28 Does the receptacle shell make multiple low impedance connections to the
chassis?
yes___ no___
EMI 29 Do the USB receptacles provide 3600 shielding of the D+ and D- signals yes___ no___
EMI 30 Does the USB receptacle provide multiple low impedance connections between
the receptacle shell and the mating connector body?
yes___ no___
Draft 15
7.2 Checklists for USB Cables
7.2.1 Checklist for Detachable USB Cables
EMI 31 Is the cable shielded? yes___ no___
EMI 32 Is the shield either copper braid or spiral copper wrap? yes___ no___
EMI 33 Does the shield provide at least 65% shield coverage? yes___ no___
EMI 34 Does the cable have a twisted data pair impedance controlled to 90W +/- 15%? yes___ no___
EMI 35 Does the cable have a type A connector on one end and a type B connector on
the other?
yes___ no___
EMI 36 Is the cable length less than 5.0 meters? yes___ no___
EMI 37 Is the gauge of the power pair between 20 and 28 Ga? This requirement is to
guarantee that the USB connector can be reliable crimped to the cable.
yes___ no___
EMI 38 Is the IR drop through VBUS and Gnd of the cable and connectors less than 250
mV @ 500 ma
yes___ no___
EMI 39 Are the connectors attached in such a manner that a 3600 crimp can be
achieved with the shield?
yes___ no___
EMI 40 Does the connector shell provide multiple low impedance sites for making
connections with the shell of the receptacle?
yes___ no___
EMI 41 Does the connector shell provide 3600 shielding between where the shield
terminates and the edge of the connector shell?
yes___ no___
7.2.2 Checklist for non-Detachable Cables to Full Speed Devices or Self Powered
Hubs
EMI 42 Is the cable shielded? yes___ no___
EMI 43 Is the shield either copper braid or spiral copper wrap? yes___ no___
EMI 44 Does the shield provide at least 65% shield coverage? yes___ no___
EMI 45 Does the cable have a twisted data pair impedance controlled to 90W +/- 20%? yes___ no___
EMI 46 Does the cable have a type A connector on one end ? yes___ no___
EMI 47 Does the shield terminate to the ground plane on the device end? yes___ no___
EMI 48 Is the cable length less than 5.0 meters? yes___ no___
EMI 49 Is the gauge of the power pair between 20 and 28 Ga? This requirement exists
because the standard USB connector will not crimp reliably onto other size
conductors,
yes___ no___
EMI 50 Are the connectors attached in such a manner that a 3600 crimp can be
achieved with the shield?
yes___ no___
EMI 51 Does the connector shell provide multiple low impedance sites for making
connections with the shell of the receptacle?
yes___ no___
EMI 52 Does the connector shell provide 3600 shielding between where the shield
terminates and the edge of the connector shell?
yes___ no___
Draft 16
7.3 Checklist for Low speed USB peripherals
7.3.1 Cabling and Connectors
EMI 53 Is the cable permanently attached to the device? yes___ no___
EMI 54 Does the cable have a type A connector on one end? yes___ no___
EMI 55 Is the cable length less than 3.0 meters? yes___ no___
EMI 56 Is the gauge of the power pair between 20 and 28 Ga? This requirement exists
because the standard USB connector will not crimp reliably onto other size
conductors,
yes___ no___
7.3.2 Electrical
EMI 57 Does the low speed device signal with edge rates between 75 and 300 ns? yes___ no___
EMI 58 Is the capacitance to gnd (including the cable) on D+ and D- less than 350pf? yes___ no___
EMI 59 Does the device signal with a bit rate of 1.5 Mb/sec +/- 1.5% yes___ no___
EMI 60 Is the on-board clock source equal to or less than 6 Mhz? yes___ no___
EMI 61 Is the on-board clock source a crystal or a ceramic resonator? yes___ no___
EMI 62 Is the crystal or resonator driven with as low energy an excitation that is
consistent with reliable operation?
yes___ no___
EMI 63 Is the crystal can tied to ground yes___ no___
EMI 64 Does the PCB area under the crystal can have a continuous conducting plane
tied to ground?
yes___ no___
EMI 65 Are there ferrite beads on VCC and Gnd where they enter the PC board? yes___ no___
EMI 66 Are there ferrite beads on D+ and D- yes___ no___
EMI 67 Are on-board devices bypassed with respect to VCC and Gnd? yes___ no___
7.3.3 Mechanical and PC Layout
EMI 68 Are the ferrite beads placed as close as possible to the USB connector? yes___ no___
EMI 69 Is the clock source located as far from the USB connector as is possible? yes___ no___
EMI 70 Are the USB D+ and D- traces located away from traces carrying high
frequency signals?
yes___ no___
EMI 71 Does the PC board have a ground plane? yes___ no___
Draft 17
7.4 Checklist for Non-hub Full Speed Peripherals
7.4.1 Cabling and Connectors
EMI 72 If the cable is permanently attached does it meet the cable requirements shown
in Section 7.2.2?
yes___ no___
EMI 73 If the cable is detachable does the device have a USB type B receptacle yes___ no___
7.4.2 Electrical
EMI 74 Are the VBUS and Gnd lines bypassed with ferrite beads? yes___ no___
EMI 75 Do D+ and D- have series termination resistors such that Z DRIVER + ZTERM =
45W?
yes___ no___
EMI 76 Is the D+ and D- PC trace impedance 90W +/- 15% yes___ no___
EMI 77 Are the USB output driver VCC pins bypassed with dedicated bypass
capacitor(s)
yes___ no___
EMI 78 Are there termination capacitors on D+ and D-? These are optional but useful
in limiting emissions.
yes___ no___
EMI 79 Does the USB controller use a crystal rather than an oscillator yes___ no___
EMI 80 Is the crystal can tied to ground yes___ no___ na___
EMI 81 Is the area under the crystal can a conductive plane that connects to the ground
plane?
yes___ no___ na___
7.4.3 Peripheral IC
EMI 82 Are all high speed lines separated by several pins from the D+ and D- USB
pins
yes___ no___
EMI 83 Does the VCC supplying the USB output drivers have one or more dedicated
power pins?
yes___ no___
EMI 84 Does the Gnd supplying the USB output drivers have one or more dedicated
power pins?
yes___ no___
EMI 85 Do the USB drivers have the necessary number of VCC and Gnd pins for ~40
ma per pair of signal pins?
yes___ no___
EMI 86 Does a hub’s upstream port signal at full speed edge rates (4.0 - 20.0 ns) for
all traffic?
yes___ no___
EMI 87 Does the USB controller use as low frequency a clock as is feasible? yes___ no___
EMI 88 Is the crystal driven with as low an excitation energy that is consistent with
reliable operation?
yes___ no___
7.4.4 PC Layout
EMI 89 Does the PCB have a ground plane yes___ no___
EMI 90 Is the ground plane unbroken and continuous yes___ no___
EMI 91 Is the USB connector or cable attachment located away from other high speed
circuitry or traces?
yes___ no___
EMI 92 Are the ferrite beads placed as close as possible to the USB connector? yes___ no___
EMI 93 Are the series resistors located as close to the driver chip as is possible? yes___ no___
EMI 94 Are The D+ and D- traces run so that they are not routed near to any traces
carrying high speed signals, such as clocks?
yes___ no___
EMI 95 Are the D+ and D- traces routed parallel to each other yes___ no___
EMI 96 Are the termination capacitors located between the USB driver chip and the
series termination resistors?
yes___ no___
EMI 97 Do the D+ and D- traces have grounded guard traces around them yes___ no___
EMI 98 Does the receptacle or header make a low impedance connection to the ground
plane?
yes___ no___
Draft 18
7.5 Checklist for Hubs
7.5.1 Edge Rates
EMI 99 Can downstream ports be configured as low or full speed on a per port basis? yes___ no___
EMI 100 Do ports that are enumerate as low speed shut off full speed downstream
signaling?
yes___ no___
EMI 101 Are full speed signaling edge rates between 4.0 and 20.0 ns on downstream
ports?
yes___ no___
EMI 102 Are low speed signaling edge rates between 75 and 300 ns on downstream
ports?
yes___ no___
EMI 103 Does a hub’s upstream port signal at full speed edge rates (4.0 - 20.0 ns) for
all traffic?
yes___ no___
7.5.2 Cabling and Connectors
EMI 104 If the cable is detachable, does upstream port have type B USB receptacle? yes___ no___
EMI 105 If the cable is permanently attached does it meet the cable requirements
described in Section 7.2.2?
yes___ no___
EMI 106 Do all downstream ports have type A receptacles? yes___ no___
EMI 107 Does the USB receptacle shell make multiple low impedance connections to
the motherboard ground plane?
yes___ no___
EMI 108 Does the receptacle shell make multiple low impedance connections to the
chassis?
yes___ no___ na___
EMI 109 Do the USB receptacles provide 3600 shielding of the D+ and D- signals yes___ no___
EMI 110 Do the USB receptacles provide multiple low impedance connections between
the connector shell and the mating connector body?
yes___ no___
7.5.3 Electrical
EMI 111 Are the D+ and D- lines bypassed with ferrite beads? yes___ no___
EMI 112 Are the VBUS and Gnd lines bypassed with ferrite beads? yes___ no___
EMI 113 Do D+ and D- have series termination resistors such that Z DRIVER + ZTERM =
45W?
yes___ no___
EMI 114 Are the D+ and D- PC trace impedances 90W +/- 15% yes___ no___
EMI 115 Are the D+ and D- traces routed parallel to each other yes___ no___
EMI 116 Do the D+ and D- traces have grounded guard traces around them yes___ no___
EMI 117 Are the USB output driver VCC pins bypassed with dedicated capacitor(s) yes___ no___
EMI 118 Are there termination capacitors to Gnd on D+ and D-? These are optional but
are effective at limiting emissions.
yes___ no___
EMI 119 Are the termination capacitors located between the USB driver chip and the
series termination resistors?
yes___ no___ na___
EMI 120 Does the USB controller use a crystal rather than an oscillator yes___ no___
EMI 121 Is the crystal driven with as low energy an excitation that is consistent with
reliable operation?
yes___ no___ na___
EMI 122 Is the crystal can tied to ground yes___ no___ na___
EMI 123 Is the PCB area under the crystal can a continuous conductive plane that is tied
to ground?
yes___ no___ na___
7.5.4 Hub IC
EMI 124 Are any high speed lines separated by several pins from the D+ and D- USB
leads?
yes___ no___
EMI 125 Does the VCC supplying the USB output drivers have one or more dedicated
power pins?
yes___ no___
EMI 126 Does the Gnd supplying the USB output drivers have one or more dedicated
power pins?
yes___ no___
EMI 127 Do the USB drivers have the necessary number of VCC and Gnd pins for ~40
ma per pair of signal pins?
yes___ no___
EMI 128 Does a hub’s upstream port signal at full speed (4.0 - 20.0 ns) for all traffic? yes___ no___
EMI 129 Does the USB controller use as low frequency a clock as is feasible? yes___ no___
7.5.5 PC Layout
EMI 130 Does the PCB have a ground plane yes___ no___
EMI 131 Is the ground plane unbroken and continuous yes___ no___
EMI 132 Are the series termination resistors located as close to the driver chip as is
possible?
yes___ no___
EMI 133 Are The D+ and D- traces run so that they are not located near to any traces
carrying high speed signals, such as clocks?
yes___ no___
EMI 134 Are the USB connectors or cable attachment located away from other high
speed circuitry or traces?
yes___ no___
EMI 135 Are the ferrite beads on D+, D-, VBUS and Gnd located as close to the USB
connector as possible?
yes___ no___
EMI 136 Does the receptacle or header make a low impedance connection to the ground
plane?
yes___ no___