寻找UWB(OFDM)和MAC层的高手加盟

xinjihr

职位名称：通信系统工程师
1．职责：
(1)用C/C++开发UWB(OFDM)接收端的核心算法；
(2)完成对性能、复杂度和存储空间需求的仿真和优化；
(3)完成定点的C优化；
(4)与‘物理层ASIC工作组’合作提出物理层ASIC架构。
2．资格：
(1)具有开发OFDM系统算法的丰富经验；
(2)精通C/C++/Matlab编程；
(3)透彻理解通信系统；
(4)具有物理层FPGA/ASIC实现的经验。
3．优先考虑：
有以下经验者：无线通信，定点优化，FPGA实现，物理层ASIC模块架构；博士学位。


Position title: Communication System Engineer
1．Responsibilities:
(1)Develop core algorithms in C/C++ for UWB (OFDM) receiver;
(2)Perform simulation tasks and optimization in performance, complexity and memory requirement;
(3)Perform fixed point C optimization;
(4)Come up with PHY ASIC architecture with PHY ASIC group.
2．Qualification:
(1)Solid experience in OFDM system algorithm development;
(2)Proficient in C/C++/Matlab programming;
(3)Thorough understanding of communication system;
(4)Experience in FPGA/ASIC implementation of PHY.
3．Priority:
Wireless communication experience;
Fixed point optimization experience;
FPGA mapping experience;.
PHY ASIC micro architecture experience;
Ph.D.

xinjihr

Position title: RFIC Engineer
1．Responsibilities:
(1)Full-time position in RFIC design;
(2)Perform detailed circuit design for RFIC building block such as mixers, PLLs, LNAs, power amplifiers;
(3)Characterize circuit performance using RF measurement equipment;
2．Qualification:
(1)Familiar with RF/analog circuit design techniques using deep-submicron CMOS technologies;
(2)RF CMOS transmitter chain (SSB mixer/driver) design experience is a plus;      RF CMOS power amplifier/driver design experience is a plus
(3)Experiences with high frequency equipment such as network analyzer, spectrum analyzer;
(4)Experiences with circuit design tools for circuit simulation and layout such as Cadence;
(5)Understanding of wireless communication system and signal processing as well as general understanding of semiconductor IC technology;
3．Priority:
MSEE or PhD in the design of RFICs.

xinjihr

职位名称：资深MAC ASIC工程师
Position title: Senior MAC ASIC Engineer

1．Responsibilities:
(1)    Develop MAC functional blocks for UWB SoC, including MAC datapath
(2)    Perform verilog coding
(3)    Support synthesis and timing closure
(4)    Support FPGA based verification

2．Qualification:
(1)   Solid experience in SoC development;
(2)   Proficient in verilog coding;
(3)   Thorough understanding of MAC;
(4)   Solid experience in ASIC front end flow
(5)   ARQ experience
(6)   ARM/MIPS integration experience

3．Priority:
MAC implementation in ASIC, including ARQ implementation
SoC development
ASIC front end design and verification
FPGA mapping and verification

xinjihr

职位名称：资深数字后端设计工程师
Position title: Senior Digital Back-end Design Engineer

Responsibilities:
1)Responsible for developing and verifying complex digital designs with emphasis on backend tasks, including Floorplan, power planning and routing, CTS, PnR, RC extraction, ECO, DRC, LVS.
2)Work with RTL designers to optimize timing/area/power of the physical design implementation and perform static timing analysis.

Qualification:
1)3-5 years experience in backend design flow with proven SOC tapeout experience.
2)Expertise in floorplan, place and routing, signal integrity, power analysis, CTS, DFT, ECO, DRC, LVS.
3)Experienced in Synopsys/Cadence) physical design tools and flows.
4)Experienced in Mentor’s Calibre flow for DRC/ERC/LVS/Antenna flow.
5)Strong timing analysis capabilities.
6)Experience with one or more scripting languages (Perl, TCL, Shell) to automate physical design flow.
7)Good analytical and debugging skills.
8)Strong written and verbal communication skills.


Required Degree: BS
Preferred Degree: MS
Preferred Major: Electrical Engineering or related discipline

xinjihr

职位名称：资深ASIC验证工程师
Position title: Senior ASIC Verification Engineer
1．Responsibilities:
1)Working within an ASIC design team to develop reusable block-level and ASIC testbenches using high-level verification language (System Verilog).
2)Develop new ASIC verification environments to support ASIC development.
3)Review RTL architectural and implementation specifications.
4)Create stimulus drivers, monitors, dataflow models, and test plans to verify function and performance of advanced SOC ASICs.
5)Define and implement code/functional coverage plans.
6)Develop testing and regression methodologies for new verification flow.
7)Incorporate reusability into all aspects of the verification environment.
8)Develop/maintain/enhance environment tools/scripts/makefiles.

2．Qualification:
1)Minimum of 3 years ASIC verification experience in a product development environment with proven ASIC design verification skills
2)Experience in using event-driven simulators like VCS
3)Fluent in Verilog for design verification
4)Experience in writing testbench using System Verilog
5)Knowledge of peripheral IP intergration (PCI, USB2.0, PCI)
6)Knowledge of AMBA/AHB/DMA
7)Experience with one or more scripting languages: Perl, TCL, Shell
8)Superior debugging skills for large ASIC designs
9)Strong written and verbal communication skills

3．Required Degree: MS
Preferred Major: Electrical Engineering or related discipline

xinjihr

有兴趣的朋友可以发送简历到xinjihr_cn@126.com
也可以加msn:xinjihr_cn@hotmail.com.
谢谢。欢迎大家推荐高手.:)