esd in silicon

andyjackcao

esd in silicon

andyjackcao

1Introduction1
1.1Background1
1.2TheESDProblem3
1.3ProtectingAgainstESD4
1.4OutlineoftheBook4
Bibliography7
2ESDPhenomenon8
2.1Introduction8
2.2ElectrostaticVoltage9
2.3Discharge11
2.4ESDStressModels12
Bibliography15
3TestMethods17
3.1Introduction17
3.2HumanBodyModel(HBM)18
3.3MachineModel(MM)27
3.4ChargedDeviceModel(CDM)28
3.5SocketDeviceModel(SDM)40
3.6Metrology,Calibration,Veri?cation42
3.7TransmissionLinePulsing(TLP)47
3.8FailureCriteria58
3.9Summary60
Bibliography61
4PhysicsandOperationofESDProtectionCircuitElements68
4.1Introduction68
4.2Resistors68
4.3Diodes70
4.4TransistorOperation77
4.5TransistorOperationunderESDConditions85
4.6ElectrothermalEffects95
4.7SCROperation98
4.8Conclusion101
Bibliography102
ESDProtectionCircuitDesignConceptsandStrategy105
5.1TheQualitiesofGoodESDProtection106
5.2ESDProtectionDesignMethods109
5.3SelectinganESDStrategy123
5.4Summary124
Bibliography124
DesignandLayoutRequirements126
6.1Introduction126
6.2ThickFieldDevice127
6.3nMOSTransistors(FPDs)132
6.4Gate-CouplednMOS(GCNMOS)138
6.5GateDrivennMOS(GDNMOS)149
6.6SCRProtectionDevice150
6.7ESDProtectionDesignSynthesis155
6.8TotalInputProtection164
6.9ESDProtectionUsingDiode-BasedDevices172
6.10PowerSupplyClamps176
6.11BipolarandBiCMOSProtectionCircuits179
6.12Summary183
Bibliography184
AdvancedProtectionDesign188
7.1Introduction188
7.2PNP-DrivennMOS(PDNMOS)188
7.2PNP-DrivennMOS(PDNMOS)188
7.3SubstrateTriggerednMOS(STNMOS)189
7.4nMOSTriggerednMOS(NTNMOS)192
7.5ESDforMixed-VoltageI/O200
7.6CDMProtection214
7.7SOITechnology215
7.8High-VoltageTransistors216
7.9BiCMOSProtection218
7.10RFDesigns219
7.11GeneralI/OProtectionSchemes220
7.12Design/LayoutErrors221
7.13Summary223
Bibliography224
8FailureModes,ReliabilityIssues,andCaseStudies228
8.1Introduction228
8.2FailureModeAnalysis229
8.3ReliabilityandPerformanceConsiderations238
8.4AdvancedCMOSInputProtection239
8.5OptimizingtheInputProtectionScheme242
8.6DesignsforSpecialApplications249
8.7ProcessEffectsonInputProtectionDesign253
8.8TotalICChipProtection255
8.9PowerBusProtection256
8.10InternalChipESDDamage258
8.11StressDependentESDBehavior263
8.12FailureModeCaseStudies267
8.13Summary271
Bibliography272
9In?uenceofProcessingonESD282
9.1Introduction282
9.2HighCurrentBehavior284
9.3CrossSectionofaMOSTransistor287
9.4Drain-SourceImplantEffects288
9.5 p-WellEffects293
9.6 n-WellEffects294
9.7EpitaxialLayersandSubstrates295
9.8GateOxides298
9.9Silicides300
9.10Contacts304
9.11InterconnectandMetalization305
9.12GateLengthDependencies306
9.13Silicon-on-Insulator(SOI)310
9.14BipolarTransistors312
9.15Diodes314
9.16Resistors315
9.17ReliabilityTrade-Offs316
9.18Summary317
Bibliography320
10DeviceModelingofHighCurrentEffects326
10.1Introduction326
10.2ThePhysicsofESDDamage327
10.3Thermal(°∞Second°±)Breakdown3
10.4AnalyticalModelsUsingtheHeatEquation335
10.5ElectrothermalDeviceSimulations339
ii CONTENTS
10.6Conclusion344
Bibliography345
11CircuitSimulationBasics,Approaches,andApplications350
11.1Introduction350
11.2ModelingtheMOSFET351
11.3ModelingBipolarJunctionTransistors367
11.4ModelingDiffusionResistors371
11.5ModelingProtectionDiodes375
11.6SimulationofProtectionCircuits376
11.7ElectrothermalCircuitSimulations382
11.8Conclusion385
Bibliography389
12Conclusion394
12.1Long-TermRelevanceofESDInICs394
12.2State-of-the-ArtforESDProtection395
12.3CurrentLimitations396
12.4FutureIssues398
Bibliography399
Index401
【文件名】:08811@52RD_ESD_in_Silicon_Integrated_Circuits.part1.rar
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