最权威的SDRAM SPEC--intel

jjj0020

1.0 Introduction.................................................................................................................................1
1.1 Objective..........................................................................................................1
1.2 Scope of This Document..................................................................................1
1.3 Convention Used .............................................................................................1
2.0 Pinout and Signal Description .....................................................................................................2
2.1 Device Pinouts .................................................................................................2
2.2 Signal Descriptions (Simplified) .......................................................................6
3.0 Basic Functional Description.......................................................................................................7
3.1 Mode Register and the Modes Required to be supported ...............................7
3.2 Command Truth Table.....................................................................................8
3.3 Address Bit Maps...........................................................................................14
3.3.1 16M Address Bit Maps For Row And Column Addresses During Commands
............................................................................................................14
3.3.2 64M Address Bit Maps For Row And Column Addresses During Commands
............................................................................................................15
3.3.3 128M Address Bit Maps For Row And Column Addresses During Commands
............................................................................................................16
3.3.4 256M Address Bit Maps For Row And Column Addresses During Commands
............................................................................................................17
3.4 Power-Up and Initialization Sequence...........................................................17
3.4.1 Power Up Sequence ......................................................................................17
3.4.2 Initialization Sequence..................................................................................18
3.5 Precharge Selected Bank ..............................................................................18
3.6 Precharge All .................................................................................................19
3.7 NOP and Device Deselect .............................................................................19
3.8 Row activate ..................................................................................................19
3.9 Read Bank .....................................................................................................20
3.10 Write Bank .....................................................................................................20
3.11 Mode Register Set Command........................................................................20
4.0 Essential Functionality for the “PC SDRAM” Device .............................................................22
4.1 Burst Read and Burst Write ...........................................................................22
4.2 Multibank Ping Pong Access .........................................................................23
4.3 Read and Write With Autoprecharge .............................................................24
4.4 Precharge Termination of Burst .....................................................................24
4.4.1 Precharge Command After a Burst Read......................................................24
4.4.2 Precharge Termination of a Burst Read........................................................25
4.4.3 Precharge Command After a Burst Write .....................................................26
4.4.4 Precharge Termination of a Burst Write .......................................................26
4.5 Read Terminated By Read ............................................................................26
4.6 Write Terminated By Write.............................................................................27
4.7 Read Terminated By Write.............................................................................27
4.8 Write Terminated By Read.............................................................................28
4.9 SDRAM Commands, To Two Or Four Banks, In Consecutive Clocks...........29
4.10 Next Command To Same Bank After Precharge...........................................29
4.10.1 Precharge Bank .............................................................................................29
4.10.2 Precharge All................................................................................................ 29
4.10.3 Read-Auto_Precharge .................................................................................. 29
4.10.4 Write-Auto_Precharge ................................................................................. 29
4.11 Concurrent Precharge Commands To Multiple Rows ................................... 29
4.12 Back to back Command With Auto Precharge .............................................. 30
4.13 DQM# Latency............................................................................................... 32
4.14 Back to Back Command Support................................................................... 32
4.15 Auto Refresh (CBR) Command ..................................................................... 32
4.16 Self Refresh Entry/Exit................................................................................... 33
4.17 Low Power ICCLP ......................................................................................... 34
4.18 Non-Required SDRAM Functionality ............................................................. 34
4.19 Multibank Operation....................................................................................... 34
5.0 Synchronous DRAM AC/DC Parameters................................................................................. 43
5.1 DC Specifications .......................................................................................... 43
5.2 A.C. Specifications......................................................................................... 45
5.3 IBIS: I/V Characteristics for Input and Output Buffers ................................... 46
5.4 IBIS Reference .............................................................................................. 51
5.5 A.C. Timing Parameters ................................................................................ 52
5.6 Device Options .............................................................................................. 54
5.7 Output Load Specification.............................................................................. 56
5.8 Active Power in Application ........................................................................... 57


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