Design and Optimization of CMOS RF Power Amplifiers

robertqi

【文件名】:08629@52RD_Design and optimization of CMOS RF power amplifiers.pdf
【格　式】:pdf
【大　小】:228K
【简　介】:Abstract—A CMOS radio-frequency power amplifier including
on-chip matching networks has been designed in a 0.6- m
n-well triple-metal digital CMOS process, and optimized using
a simulated-annealing-based custom computer-aided design
tool. A compact inductor model enables the incorporation of
parasitics as an integral part of the parasitic-aware design and
CAD optimization; low-Q metal3 spiral inductors are used in the
input and output matching networks. A 3-V 85 -mW balanced
fully integrated Class-C power amplifier with a measured drain
efficiency of 55% at 900 MHz has been designed, optimized,
integrated, and tested.
Index Terms—CMOS analog integrated circuits, CMOSFET
power amplifiers, power amplifiers, simulated annealing.
【目　录】: