【上海】招聘ASIC Logical Design & Verification Engineer

gongxiaochan

cisco上海研发中心诚聘ASIC MicroDesign and Verification Engineer 1-2名，要求：
1、重点大学毕业；
2、有大型外企经验优先；
3、英语口语流利。

具体职位要求如下：

JOB TITLE: ASIC MicroDesign and Verification Engineer[/COLOR]

Participate in the design of complex, high-performance, and highly integrated Network Processor chips used in Cisco's networking products. Responsibilities will include micro-architecture and logic design in Verilog. In addition, you will apply your experience in high-speed design timing closure to help partition the design to meet physical design and timing constraints. Work closely with those performing the physical implementation of the design. You will also participate in establishing methodologies for power/clock distribution, timing closure, static timing analysis, power analysis, and generally help to bridge logic design concepts to back-end physical design requirements.

RESPONSIBILITIES
•Defining and analyzing architecture and feasibility studies.
•Detailed micro-architecture specification, RTL logic design, synthesis and timing closure.
•Develop test plans, participate in reference model development and RTL verification and debug.
•Participating in reference model development, logic verification, synthesis, formal verification and static timing analysis.

SKILLS AND EXPERIENCE
•MSEE/CS combined with 1-3 years of related experience, or BSEE/CS combined with 2-4 years related experience.
•Experience in high-performance ASIC design.
•Good understanding of ASIC methodologies and flows.
•Hands-on experience with HDL (Verilog, SystemVerilog) and tools, scripting and programming languages (Perl, TCL, C++). .cn

•Can make design tradeoffs between logical and physical design to optimize for logical requirements, physical complexity, speed, area, power and schedule.
•Knowledge in network protocol and experience in switch and router architect.

请有意向的朋友速速与我联系哦！
联系人：shirley
Tel: 021-63601166-616
Email: shirley.gong@e4u
MSN： gongchanyuan@hotmail.com[/COLOR]