Scalable MPEG-4 Encoder on FPGA Multiprocessor SOC

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【文件名】:0853@52RD_Scalable MPEG-4 Encoder on FPGA Multiprocessor SOC.rar
【格　式】:rar
【大　小】:687K
【简　介】:High computational requirements combined with rapidly evolving video coding algorithms and standards are a great challenge
for contemporary encoder implementations. Rapid specification changes prefer full programmability and configurability both for
software and hardware. This paper presents a novel scalable MPEG-4 video encoder on an FPGA-based multiprocessor systemon-
chip (MPSOC). The MPSOC architecture is truly scalable and is based on a vendor-independent intellectual property (IP)
block interconnection network. The scalability in video encoding is achieved by spatial parallelization where images are divided
to horizontal slices. A case design is presented with up to four synthesized processors on an Altera Stratix 1S40 device. A truly
portable ANSI-C implementation that supports an arbitrary number of processors gives 11 QCIF frames/s at 50MHz without
processor specific optimizations. The parallelization efficiency is 97% for two processors and 93% with three. The FPGA utilization
is 70%, requiring 28 797 logic elements. The implementation effort is significantly lower compared to traditional multiprocessor
implementations.
【目　录】: