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本人為學生 正在為畢業研究努力
本人寫了一個測試ARM7TDMI 的中斷程式 但是無法發生中斷...
這個程式是想用TIMER5 的1ms 時段發生中斷,在每一次中斷時將i ++ (使用TIMER的固定時段中斷)
在MAIN 中則利用I的變化來進行多種工作;(以下只是用BEEP 來測試是否成功)
因為本人不太清楚ISR的寫法 也不太清楚先後次序的設定 但因為只有1個中斷所以也就沒管了...
以下是程式...
#include "option.h"
#include "def.h"
#include "44b.h"
#include "44blib.h"
void T5_start(void);
void __irq T1_ISR(void);
U8 count;
void InitInt (void);
int Main (void)
{
U32 TCFG0=0;
rSYSCFG=CACHECFG; // Using 8KB Cache//
ChangePllValue(248,12,2); // (MDIV,PDIV,SDIV) O/P Freq from PLL block 45.7MHZ, Port_Init();
Port_Init;
Beep(0);
InitInt();
pISR_TIMER1=(int)T1_ISR;
// -------------------------------------- Timer config --------------------------------------------
TCFG0 &= 0xFF39FFFF;
TCFG0 |= 0x390000; // T5 prescaler =57
rTCFG0 = TCFG0;
while (1) {
if (count >40)
Beep(1);
else
Beep(0);
}
}
// ------------------------------------------ ISR -------------------------------------------------
void __irq T1_ISR(void)
{
rI_ISPC =0x1000 ; // INT_TIMER1 pending bit clear
{
count++;
if (count >=50)
count=0;
}
}
void T1_start(void)
{
U32 TCON=0;
rTCNTB5 = 0x18A; // 394x duty cycle(2.5383us) = 1ms
TCON =0xA00 // config T1(auto reload,manual update = 1),update TCNTB1to TCNT1;
rTCON = TCON;
Delay(10);
TCON =0x900; // disable manual updata the TCNTB1, enable timer
rTCON = TCON;
}
void InitInt (void)
{
#define V 0 // 0 = Vectored interrupt mode 1 = Non-vectored interrupt mode
#define I 0 // 0 = IRQ interrupt enable
#define F 1 // 0 = FIQ interrupt enable (Not allowed vectored interrupt mode) 1 = Reserved
rINTCON = ((V<<2)+(I<<1)+F);
// EINT0 EINT1 EINT2 EINT3 EINT4567 TICK ZDMA0 ZDMA1 BDMA0 BDMA1 WDT UERR0/1 TIMER0 TIMER1 TIMER2 TIMER3 TIMER4 TIMER5 URXD0 URXD1 IIC SIO UTXD0 UTXD1 RTC ADC.
// 0 = IRQ mode 1 = FIQ mode
rINTMOD = ((0<<25)+(0<<24)+(0<<23)+(0<<22)+(0<<21)+(0<<20)+(0<<19)+(0<<18)+(0<<17)+(0<<16)+(0<<15)+(0<<14)+(0<<13)+(1<<12)+(0<<11)+(0<<10)+(0<<9)+(0<<8)+(0<<7)+(0<<6)+(0<<5)+(0<<4)+(0<<3)+(0<<2)+(0<<1)+0);
// 0 = Service available 1 = Masked
rINTMSK = ((0<<26)+(0<<25)+(0<<24)+(0<<23)+(0<<22)+(0<<21)+(0<<20)+(1<<19)+(1<<18)+(1<<17)+(1<<16)+(1<<15)+(1<<14)+(1<<13)+(0<<12)+(1<<11)+(1<<10)+(1<<9)+(1<<8)+(1<<7)+(1<<6)+(1<<5)+(1<<4)+(1<<3)+(1<<2)+(1<<1)+1);
// IRQ priority of slave register
rI_PSLV = 0x1b1b1b1b;
// IRQ priority of master register
rI_PMST = 0x00001f1b;
// IRQ interrupt service pending clear register
rI_ISPC = 0xffffffff;//I_ISPR; // Clear all pending.
// FIQ interrupt service pending clear register
rF_ISPC = rF_ISPR; // Clear all pending.
rEXTINTPND = 0x0f; // External(4,5,6,and 7) interrupt pending Register. cleared by writing 1.
}
在這請求各位幫忙[em03] |
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