集成电路设计 英文书籍

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介绍集成电路设计的英文原版书籍，希望对大家有用。

书名为 a_top_down_approach_to_ic_design

【文件名】:0841@52RD_集成电路设计.rar
【格　式】:rar
【大　小】:698K
【简　介】:集成电路设计
【目　录】:
Preface Overview ...................................................................................................1
Organization of This Document ................................................................2
1
Introduction Introduction ........................................................................................... 1-1
What is Top-Down Design? .................................................................. 1-2
The Bottom-Up Design Approach .................................................. 1-2
The Top-Down Design Approach ................................................... 1-2
Success Factors in the Transition to Top-Down Design ....................... 1-4
Advances in Semiconductor Technology ....................................... 1-5
Advances in EDA Technology ....................................................... 1-6
The Challenge to Productivity ........................................................ 1-7
Example of Top- Down Design Success ...................................... 1-19
Basic Principles of Top-Down Design ............................................... 1-20
The Top-Down Design Flow and Schedule ........................................ 1-22
Summary ............................................................................................. 1-26
References ........................................................................................... 1-27
2
Design
Environment
Methodology
Design Environment: the Challenges .................................................... 2-1
Design Data Organization ..................................................................... 2-2
Source Control ...................................................................................... 2-4
Configuration Management .................................................................. 2-5
Automated Procedures .......................................................................... 2-6
Revision Control ................................................................................... 2-7
Bug Tracking ........................................................................................ 2-8
References ............................................................................................. 2-9
ii A Top-Down Approach To IC Design v1.1
3
Design
Environment
Implementation
Overview ............................................................................................... 3-1
Design Data Organization ..................................................................... 3-2
File Naming Conventions ............................................................... 3-4
Source Control ...................................................................................... 3-5
Checking In a File ........................................................................... 3-5
Checking Out a File ........................................................................ 3-6
Configuration Management .................................................................. 3-7
HDL Design Configurations ........................................................... 3-7
HDL Simulation Configurations ..................................................... 3-9
Automated Procedures ........................................................................ 3-10
Tracking Bugs ..................................................................................... 3-12
Using the Design Environment ........................................................... 3-13
References ........................................................................................... 3-14
Lab ..................... Exercise: Introduction to the Design Environment 3-15
4
Design Capture
Methodology
Design Capture: The Challenge ............................................................ 4-1
The Goals of Design Capture ................................................................ 4-2
Behavioral HDL Models ................................................................. 4-5
RTL Implementation Models .......................................................... 4-6
Structural Models ............................................................................ 4-6
System Models ...................................................................................... 4-8
System Specifications ..................................................................... 4-8
Analytic Models ............................................................................ 4-10
Behavioral System Models ........................................................... 4-13
RTL Implementation Models .............................................................. 4-14
Synthesis Modeling Style ............................................................. 4-14
Hierarchical Designs ..................................................................... 4-16
Structural Models .......................................................................... 4-18
Datapath Design ............................................................................ 4-19
Design Capture Technologies ............................................................. 4-21
References ........................................................................................... 4-23
v1.1 iii
4
Design for Test
Methodology
Design for Test: the Challenge ............................................................. 5-1
Goals of a DFT Methodology ............................................................... 5-2
Structured DFT Techniques .................................................................. 5-3
Internal Scan ................................................................................... 5-5
Boundary Scan ................................................................................ 5-5
Test Access Collar .......................................................................... 5-8
Built-In Self Test for RAMs ........................................................... 5-9
Iddq Testing ................................................................................... 5-10
Delay Fault Testing ....................................................................... 5-13
DFT Rules and Guidelines .................................................................. 5-15
References ........................................................................................... 5-17
6
DesignVerification
Methodology
Design Verification: the Challenge ....................................................... 6-1
Design Verification Goals ..................................................................... 6-4
Validating System Intent ....................................................................... 6-5
Analyzing System Performance ...................................................... 6-5
Verifying System Functionality ...................................................... 6-7
Verifying the Partitioning and Packaging ....................................... 6-7
Verifying the Implementation ............................................................... 6-8
Using Appropriate Verification Technologies .............................. 6-11
Choosing the Appropriate Tests .................................................... 6-12
Developing Structured Testbenches ............................................. 6-17
Setting Up Verification Procedures .............................................. 6-20
References ........................................................................................... 6-25
7
High-Level System
Design
Process Overview .................................................................................. 7-1
Design Environment ....................................................................... 7-2
System Design ................................................................................ 7-2
Firmware ......................................................................................... 7-2
iv A Top-Down Approach To IC Design v1.1
Design Modeling and Verification .................................................. 7-3
Logic Design ................................................................................... 7-3
Design-for-Test ............................................................................... 7-3
Timing Driven Physical Design ...................................................... 7-3
System Specification ............................................................................. 7-7
Algorithm Development ....................................................................... 7-9
Performance Analysis ......................................................................... 7-17
System Partitioning ............................................................................. 7-19
Functional Specification ..................................................................... 7-20
Serial Port Interface (SPI) ............................................................. 7-20
DMA Controller (DMA) ............................................................... 7-21
Memory Access Bus Arbiter (ARB) ............................................. 7-21
u-Law PCM to Linear PCM Conversion (ULAW_LIN_CONV) . 7-22
Digital Signal Processor (DSP) ..................................................... 7-22
Results Character Conversion (RCC) ........................................... 7-25
ASCII Digit Register (DIGIT_REG) ............................................ 7-25
Memory Map ................................................................................ 7-25
Design Verification Strategy ............................................................... 7-27
High Level Floorplanning ................................................................... 7-29
DFT Planning and Specification ......................................................... 7-30
DFT Strategy and Testability Analysis ......................................... 7-31
DFT Design Considerations .......................................................... 7-31
Tester Resource Considerations .................................................... 7-32
References ........................................................................................... 7-34
Exercises ............................................................................................. 7-35
8
Logic Synthesis
Methodology
Synthesis: The Challenge ...................................................................... 8-1
Goals of a Synthesis Methodology ....................................................... 8-2
Applying the Synthesis Technology ..................................................... 8-3
Using Datapath Generators ................................................................... 8-6
Synthesizing Large Subsystems ............................................................ 8-8
Block-Level Synthesis .................................................................... 8-9
Multiblock-Level Synthesis .......................................................... 8-10
v1.1 v
Subsystem-Level Synthesis .......................................................... 8-11
Selecting the Delay Calculation Algorithm ........................................ 8-13
Linear Delay Model ...................................................................... 8-13
Nonlinear Delay Model ................................................................. 8-17
References ........................................................................................... 8-18
9
Timing-Driven
Design
Methodology
Timing: The Challenge ......................................................................... 9-1
Goals of a Timing-Driven Design Methodology .................................. 9-4
Floorplanning and Placement ............................................................... 9-5
High-Level Floorplans .................................................................... 9-6
Detailed Floorplanning ................................................................... 9-7
Timing-Driven Synthesis ...................................................................... 9-9
Accurate Timing Constraints .......................................................... 9-9
Wire Models .................................................................................. 9-12
Accurate Load Constraints ............................................................ 9-12
Estimated Parasitics ...................................................................... 9-15
Placement and Route ........................................................................... 9-16
Synthesis Back-Annotation ................................................................. 9-19
Performing Early Delay Estimation .................................................... 9-20
Timing Verification ............................................................................ 9-21
References ........................................................................................... 9-23
10
Block-Level
Implementation
Overview ............................................................................................. 10-1
Subsystem Partitioning ....................................................................... 10-4
RTL Models ........................................................................................ 10-5
Tiny Digital Signal Processor ....................................................... 10-5
Results Character Converter ......................................................... 10-8
Macro Blocks .............................................................................. 10-10
Design Verification ........................................................................... 10-12
Design Planning ................................................................................ 10-13
Implementation ................................................................................. 10-14
vi A Top-Down Approach To IC Design v1.1
DFT Logic Design and Verification ................................................. 10-21
Block-Level DFT Synthesis and Insertion .................................. 10-21
Scan Path and Test Function Verification .................................. 10-22
References ......................................................................................... 10-23
Lab Exercise: Design Entry, Simulation, and Synthesis ................... 10-24
Lab Exercise: Functional Verification .............................................. 10-27
Lab Exercise: Verification Strategies (Pattern Capture) ................... 10-28
Lab Exercise: Verification Strategies (Pattern Compare) ................. 10-29
Lab Exercise: Hardware/Firmware Co-Verification ......................... 10-30
Lab Exercise: Design Capture .......................................................... 10-35
Lab Exercise: Initial Synthesis .......................................................... 10-37
Lab Exercise: Delay Calculation ...................................................... 10-38
Lab Exercise: Constraint Derivation ................................................. 10-39
Lab Exercise: Timing Analysis ......................................................... 10-42
Lab Exercise: Optimization Strategies .............................................. 10-43
Lab Exercise: Resource Sharing ....................................................... 10-44
Lab Exercise: Macro Libraries .......................................................... 10-46
Lab Exercise: Test Insertion ............................................................. 10-47
11
Chip-Level
Assembly
Implementation
Overview ............................................................................................. 11-1
Logical Chip Assembly ....................................................................... 11-4
Chip-Level DFT Synthesis and Insertion ..................................... 11-4
Scan Chains ................................................................................... 11-5
RAM BIST .................................................................................... 11-6
Boundary Scan and TAP Controller ............................................. 11-7
Functional Verification ....................................................................... 11-8
Hardware Verification .................................................................. 11-8
Software Verification .................................................................. 11-11
Drive Optimization ........................................................................... 11-14
Gate Level Verification ..................................................................... 11-17
Detailed Floorplanning ..................................................................... 11-18
Timing Optimization / Resizing ....................................................... 11-19
Static Timing Analysis ...................................................................... 11-20
v1.1 vii
Design Rule Check ........................................................................... 11-27
Test Development and Validation .................................................... 11-28
ASIC Test Vector Suite .............................................................. 11-28
Functional Test Development ..................................................... 11-31
Automatic Test Pattern Generation ............................................. 11-31
Test Vector Verification ............................................................. 11-33
Tester Formatting and Hand-Off ................................................ 11-33
Final Placement and Route ............................................................... 11-35
References ......................................................................................... 11-37
A
Programming with
the TDSP
TDSP Instruction Set ........................................................................... A-1
TDSP Assembler ................................................................................ A-16
Source Statement Syntax ............................................................. A-16
Define Assembly Time Constant Attribute .................................. A-17
Constants ...................................................................................... A-17
Initialize Word Attribute .............................................................. A-17
Absolute Origin Attribute ............................................................ A-18
Predefined Symbols and Abbreviations ....................................... A-18
B
GNU Free
Documentation
License
GNU Free Documentation License .......................................................B-3







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