【上海】展讯通信招聘ASIC Synthesis Engineer及ASIC DFT Engineer

JessieJJ

两个职位具体描述请见如下：

ASIC Synthesis Engineer
Responsibilities:
        Responsible for digital logic synthesis, STA and formal verification.
        Build up and maintain related flow and script templates.

Qualifications:
        Proficiency in logic synthesis, STA and formal verification.
        Experience with DesignCompiler, PrimeTime and Formality.
        Proficiency in Verilog language.
        Experience with logic design and simulation.
        Experience with 90nm or 65nm process is a plus.
        Good knowledge of SOC design is a plus.
        At least two chip sign-off experience.
        Self-motivated and good team player.
        MSEE with 2+ years or BSEE with 4+ years.


ASIC DFT Engineer

Responsibilities:
        Responsible for whole chip DFT plan defining.
        Responsible for scan-insertion and ATPG.
        Responsible for RAM/ROM BIST and other black-box testing.
        Also responsible for test pattern debugging on ATE.

Qualifications:
        Proficiency in DFT plan defining.
        Proficiency in scan-insertion and ATPG.
        Proficiency in BIST generating.
        Proficiency in test pattern debugging on ATE.
        Experience with DFT and Synthesis tools.
        Proficiency in Verilog language.
        Experience with logic design and synthesis.
        Experience with 90nm or 65nm process is a plus.
        Good knowledge of SOC design is a plus.
        At least one chip sign-off experience.
        Self-motivated and good team player.
        MSEE with 2+ years or BSEE with 4+ years.

有意向者可将简历发送至 recruiting@163.com

谢谢大家！