【上海】美资上市公司寻找ASIC设计和验证人才

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公司简介:美国上市公司，现在全球最大的无线网卡芯片供应商之一,持续在WLAN市场上保持着技术与市占率优势，致力于成为802.11n标准及其产品的领导者。
目前该公司的技术实力非常强大，已经处于引导标准的阶段-----做标准的公司的必然有光明的前途！
五家顶级PC制造商中有四家将在其笔记本电脑中安装该公司的芯片组，以实现WLAN功能，足见其实力！最大最好的的客户自然带来最大最好的市场！
未来的世界是无线的世界，无线的产品必然会有更加广阔的应用空间。
1.ASIC设计
Job Overview:
The Digital Design Engineer will be responsible for designing our Ethernet NIC/Switch and SOC ASIC's. You will work closely with our architecture/algorithm engineers to explore ideas for next generation products and then develop RTL to tern these ideas into customer solutions.

Duties/Responsibilities:
Chip features specification and RTL design
Synthesis, verification, timing.
FPGA emulation, lab validation and debugging.

Qualifications:
BS in Electrical/Electronics Engineering, MS preferred.
3 years experience with Verilog programming, logic synthesis and gate timing. A proven record of delivering successful ASIC's to the market is preferred.
One or more advantages as following are highly desirable: A strong background in digital communication and networking protocols; IC Design experiences in Ethernet NIC or switches; Experiences with PCIe.  
Good communication skills in English.

Skills/Experience:
Must be proficient in RTL coding, logic synthesis, gate-level simulations.
Good knowledge of IC design backend flows.
Experiences in IC life-cycle from conception, design, verification, top-level netlist with pads to tape-out, chip-testing and mass-production.
FPGA, PCB or embedded SW skill is a plus.
2. Digital Verification Engineer
Job Overview:
The Digital Verification Engineer will be responsible for the simulation and verification to craft our
wireless and SoC ASICs. This position requires working with our architecture/algorithm and design
engineers to prove correctness and measure performance of our algorithms and RTL.
Responsibilities include developing simulation environments used by our test development team to exercise
Matlab and Verilog models, as well as evaluate third party tools and develop methodologies which enhance
our ability to produce high quality ASICs.

Duties/Responsibilities:
Developing simulation environments, and evaluate third party tools and develop efficient methodologies.
Design directed and random simulations to exercise Matlab and Verilog models.
FPGA emulation, lab validation and debugging.

Qualifications:
BS in Electrical/Electronics Engineering, MS preferred.
3 years experience with various verification flows is required, with a proven track record of delivering
successful ASICs.
A strong background in software is a must, along with familiarity with ASIC design flows.
Good communication skills in English.
Skills/Experience:
Strong background and experience required in C/C++, Verilog, and ASIC verification techniques.
Must be proficient in one or more major verification languages, such as Vera, Speceman, System C.
Experience in the area of automatic code generation is a plus. Perl and Unix Shell experience is a plus.
Good knowledge of IC design backend flows.
FPGA, PCB or embedded SW skill is a plus.